Patents by Inventor Calto Wong

Calto Wong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7003682
    Abstract: In an electronic device, a first electronic circuit is selectively operated in a selected one of at least two operating modes. A second electronic circuit is selectively operated in a power-up mode and a power-down mode. The second electronic circuit is put into the power-down mode if the first electronic circuit is operated in one of the at least two operating modes.
    Type: Grant
    Filed: July 17, 2001
    Date of Patent: February 21, 2006
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Jean-Marc Irazabal, Calto Wong
  • Publication number: 20030016066
    Abstract: In an electronic device, a first electronic circuit is selectively operated in a selected one of at least two operating modes. A second electronic circuit is selectively operated in a power-up mode and a power-down mode. The second electronic circuit is put into the power-down mode if the first electronic circuit is operated in one of the at least two operating modes.
    Type: Application
    Filed: July 17, 2001
    Publication date: January 23, 2003
    Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V.
    Inventors: Jean-Marc Irazabal, Calto Wong
  • Patent number: 6393572
    Abstract: In a master-slave configuration wherein a sleepmode activation is effected by the cessation of a clocking signal, the need for an analog device or auxiliary clock for detecting the cessation of the clocking signal is obviated by anticipating the cessation of the clock signal. Upon anticipating the cessation of the clock signal, the remaining clock signaling before cessation is used as required to effect a controlled power-down of the slave device. By eliminating the need for an analog clock cessation detector, the process tolerance constraints associated with analog circuitry can be avoided, the reliability and robustness of the design is improved, and the required testing is simplified, thereby reducing the cost of the device. In like manner, the elimination of an auxiliary clock generator reduces the cost and complexity of the device and system, and improves the device and system's overall reliability and testability.
    Type: Grant
    Filed: April 28, 1999
    Date of Patent: May 21, 2002
    Assignee: Philips Electronics North America Corporation
    Inventors: Dev Datta, Rune H. Jensen, Calto Wong, Daisuke Takise
  • Patent number: 6249829
    Abstract: A communication bus system is disclosed. More particularly, the communication bus system includes requesting stations that can issue request packets via a bus and an execution station. The execution station receives the request packets and executes commands modifying the same aspect of a state of the execution station in response to request packets from different stations. The execution station keeps information concerning execution of commands which were last executed in response to request packets for all the different requesting stations. The requesting stations can read this information to determine whether the commands corresponding to their packets are executed, even when other requesting stations are also issuing request packets. Preferably, the execution station shows each requesting station only the information about the execution of commands executed to its own request packets.
    Type: Grant
    Filed: September 10, 1998
    Date of Patent: June 19, 2001
    Assignee: U.S. Philips Corporation
    Inventors: Rudolf H. J. Bloks, Calto Wong