Patents by Inventor Calvin Gabriel
Calvin Gabriel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9922833Abstract: Semiconductor devices and methods of manufacturing such devices are described herein. According to embodiments, the semiconductor device can be made by forming a dielectric layer at a first region and at a second region of a semiconductor substrate. A gate conductor layer is disposed over the dielectric formed in the first and the second regions of the semiconductor substrate, and the second region is masked. A split gate memory cell is formed in the first region of the semiconductor substrate with a first gate length. The first region is then masked, and the second region is etched to define a logic gate that has a second gate length. The first and second gate lengths can be different.Type: GrantFiled: December 16, 2015Date of Patent: March 20, 2018Assignee: Cypress Semiconductor CorporationInventors: Mark Ramsbey, Chun Chen, Sameer Haddad, Kuo Tung Chang, Unsoon Kim, Shenqing Fang, Yu Sun, Calvin Gabriel
-
Publication number: 20160111292Abstract: Semiconductor devices and methods of manufacturing such devices are described herein. According to embodiments, the semiconductor device can be made by forming a dielectric layer at a first region and at a second region of a semiconductor substrate. A gate conductor layer is disposed over the dielectric formed in the first and the second regions of the semiconductor substrate, and the second region is masked. A split gate memory cell is formed in the first region of the semiconductor substrate with a first gate length. The first region is then masked, and the second region is etched to define a logic gate that has a second gate length. The first and second gate lengths can be different.Type: ApplicationFiled: December 16, 2015Publication date: April 21, 2016Applicant: Cypress Semiconductor CorporationInventors: Mark RAMSBEY, Chun CHEN, Sameer HADDAD, Kuo Tung CHANG, Unsoon KIM, Shenqing FANG, Yu SUN, Calvin GABRIEL
-
Publication number: 20140167141Abstract: Semiconductor devices and methods of manufacturing such devices are described herein. According to embodiments, the semiconductor device can be made by forming an dielectric layer at a first region and at a second region of a semiconductor substrate. A gate conductor layer is disposed over the dielectric formed in the first and the second regions of the semiconductor substrate, and the second region is masked. A split gate memory cell is formed in the first region of the semiconductor substrate with a first gate length. The first region is then masked, and the second region is etched to define a logic gate that has a second gate length. The first and second gate lengths can be different.Type: ApplicationFiled: December 14, 2012Publication date: June 19, 2014Applicant: Spansion LLCInventors: Mark RAMSBEY, Chun CHEN, Sameer HADDAD, Kuo Tung CHANG, Unsoon KIM, Shenqing FANG, Yu SUN, Calvin GABRIEL
-
Patent number: 8035153Abstract: A method for fabricating a memory device with a self-aligned trap layer which is optimized for scaling is disclosed. In the present invention, a non-conformal film is deposited over the charge trapping layer to form a thick film on top of the core source/drain region and a pinch off and a void or a narrow channel at the top of the STI trench. An etch is performed on the non-conformal film to open pinch-off or widen the narrow channel in the non-conformal. The trapping layer is then completely or partially etched between the core cells. The non-conformal film is removed. And a top oxide is formed. The top oxide converts the remaining trap layer to oxide if the trapping layer is partially etched and thus isolate the trap layer.Type: GrantFiled: May 26, 2010Date of Patent: October 11, 2011Assignee: Spansion LLCInventors: Shenqing Fang, Jihwan Choi, Calvin Gabriel, Fei Wang, Angela Hui, Alexander Nickel, Zubin Patel, Phillip Jones, Mark Chang, Minh-Van Ngo
-
Patent number: 7906807Abstract: Memory devices having improved TPD characteristics and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The bit line dielectrics can extend into the semiconductor. The memory cell contains one or more charge storage nodes, a first poly gate, a pair of first bit lines, and a pair of second bit lines. The second bit line can be formed at a higher energy level, a higher concentration of dopants, or a combination thereof compared to an energy level and a concentration of dopants of the first bit line.Type: GrantFiled: June 30, 2010Date of Patent: March 15, 2011Assignee: Spansion LLCInventors: Ning Cheng, Calvin Gabriel, Angela Hui, Lei Xue, Harpreet Kaur Sachar, Phillip Lawrence Jones, Hiro Kinoshita, Kuo-Tung Chang, Huaqiang Wu
-
Publication number: 20100264480Abstract: Memory devices having improved TPD characteristics and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The bit line dielectrics can extend into the semiconductor. The memory cell contains one or more charge storage nodes, a first poly gate, a pair of first bit lines, and a pair of second bit lines. The second bit line can be formed at a higher energy level, a higher concentration of dopants, or a combination thereof compared to an energy level and a concentration of dopants of the first bit line.Type: ApplicationFiled: June 30, 2010Publication date: October 21, 2010Applicant: SPANSION LLCInventors: Ning Cheng, Calvin Gabriel, Angela Hui, Lei Xue, Harpreet Kaur Sachar, Phillip Lawrence Jones, Hiro Kinoshita, K.T Chang, Huaqiang Wu
-
Publication number: 20100230743Abstract: A method for fabricating a memory device with a self-aligned trap layer which is optimized for scaling is disclosed. In the present invention, a non-conformal film is deposited over the charge trapping layer to form a thick film on top of the core source/drain region and a pinch off and a void or a narrow channel at the top of the STI trench. An etch is performed on the non-conformal film to open pinch-off or widen the narrow channel in the non-conformal. The trapping layer is then completely or partially etched between the core cells. The non-conformal film is removed. And a top oxide is formed. The top oxide converts the remaining trap layer to oxide if the trapping layer is partially etched and thus isolate the trap layer.Type: ApplicationFiled: May 26, 2010Publication date: September 16, 2010Inventors: Shenqing Fang, Jihwan Choi, Calvin Gabriel, Fei Wang, Angela Hui, Alexander Nickel, Zubin Patel, Phillip Jones, Mark Chang, Minh-Van Ngo
-
Patent number: 7776688Abstract: Memory devices having improved TPD characteristics and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The bit line dielectrics can extend into the semiconductor. The memory cell contains one or more charge storage nodes, a first poly gate, a pair of first bit lines, and a pair of second bit lines. The second bit line can be formed at a higher energy level, a higher concentration of dopants, or a combination thereof compared to an energy level and a concentration of dopants of the first bit line.Type: GrantFiled: August 8, 2007Date of Patent: August 17, 2010Assignee: Spansion LLCInventors: Ning Cheng, Calvin Gabriel, Angela Hui, Lei Xue, Harpreet Kaur Sachar, Phillip Lawrence Jones, Hiro Kinoshita, Kuo-Tung Chang, Huaqiang Wu
-
Patent number: 7732276Abstract: A method for fabricating a memory device with a self-aligned trap layer which is optimized for scaling is disclosed. In the present invention, a non-conformal film is deposited over the charge trapping layer to form a thick film on top of the core source/drain region and a pinch off and a void or a narrow channel at the top of the STI trench. An etch is performed on the non-conformal film to open pinch-off or widen the narrow channel in the non-conformal. The trapping layer is then completely or partially etched between the core cells. The non-conformal film is removed. And a top oxide is formed. The top oxide converts the remaining trap layer to oxide if the trapping layer is partially etched and thus isolate the trap layer.Type: GrantFiled: April 26, 2007Date of Patent: June 8, 2010Assignee: Spansion LLCInventors: Shenqing Fang, Jihwan Choi, Calvin Gabriel, Fei Wang, Angela Hui, Alexander Nickel, Zubin Patel, Phillip Jones, Mark Chang, Minh-Van Ngo
-
Publication number: 20090042378Abstract: Memory devices having improved TPD characteristics and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The bit line dielectrics can extend into the semiconductor. The memory cell contains one or more charge storage nodes, a first poly gate, a pair of first bit lines, and a pair of second bit lines. The second bit line can be formed at a higher energy level, a higher concentration of dopants, or a combination thereof compared to an energy level and a concentration of dopants of the first bit line.Type: ApplicationFiled: August 8, 2007Publication date: February 12, 2009Applicant: SPANSION LLCInventors: Ning Cheng, Calvin Gabriel, Angela Hui, Lei Xue, Harpreet Kaur Sachar, Phillip Lawrence Jones, Hiro Kinoshita, K.T. Chang, Huaqiang Wu
-
Patent number: 7468296Abstract: In fabricating an electronic structure, a substrate is provided, and a first barrier layer is provided on the substrate. A germanium thin film diode is provided on the first barrier layer, and a second barrier layer is provided on the germanium thin film diode. A memory device is provided over and connected to the second barrier layer.Type: GrantFiled: November 30, 2005Date of Patent: December 23, 2008Assignees: Spansion LLC, Advanced Micro Devices Inc.Inventors: Ercan Adem, Matthew Buynoski, Robert Chiu, Bryan Choo, Calvin Gabriel, Joong Jeon, David Matsumoto, Jeffrey Shields, Bhanwar Singh, Winny Stockwell, Wen Yu
-
Publication number: 20080265301Abstract: A method for fabricating a memory device with a self-aligned trap layer which is optimized for scaling is disclosed. In the present invention, a non-conformal film is deposited over the charge trapping layer to form a thick film on top of the core source/drain region and a pinch off and a void or a narrow channel at the top of the STI trench. An etch is performed on the non-conformal film to open pinch-off or widen the narrow channel in the non-conformal. The trapping layer is then completely or partially etched between the core cells. The non-conformal film is removed. And a top oxide is formed. The top oxide converts the remaining trap layer to oxide if the trapping layer is partially etched and thus isolate the trap layer.Type: ApplicationFiled: April 26, 2007Publication date: October 30, 2008Inventors: Shenqing Fang, Jihwan Choi, Calvin Gabriel, Fei Wang, Angela Hui, Alexander Nickel, Zubin Patel, Phillips Jones, Mark Chang, Minh-Van Ngo
-
Publication number: 20050121738Abstract: An apparatus and a method of fabricating a semiconductor device including the steps of forming a gate dielectric layer on a semiconductor substrate; forming a gate electrode over the gate dielectric layer wherein the gate electrode defines a channel interposed between source/drain regions formed within an active region of the semiconductor substrate; and forming contact etch resistant spacers on sidewalls of the gate electrode and sidewalls of the gate dielectric layer, the contact etch resistant spacers are of a non-silicon oxide and a non-nitride material.Type: ApplicationFiled: December 3, 2003Publication date: June 9, 2005Inventors: Calvin Gabriel, Christopher Lyons, Marina Plat, Ramkumar Subramanian
-
Publication number: 20050073021Abstract: The selective etch shallow trench isolation barrier integrated circuit fabrication system and method of the present invention minimizes the layers required to implement a shallow trench isolation barrier in an integrated circuit. A selective etch shallow trench isolation barrier integrated circuit in which a selective etch shallow trench isolation barrier is adjacent to an intermetal dielectric layer. Etching space in the intermetal dielectric layer for a contact plug is performed in a single film layer etch step. The selective etch shallow trench isolation barrier includes selective etch isolation material able to both withstand etching processes directed toward the insulation layer (e.g., to create a space for a contact plug) and facilitate isolation of devices from outside electrical influences. A present invention selective etch shallow trench isolation barrier integrated circuit does not require a shallow trench isolation barrier etch stop layer.Type: ApplicationFiled: May 10, 2004Publication date: April 7, 2005Inventors: Calvin Gabriel, Edward Yeh
-
Patent number: 6713382Abstract: A method of manufacturing a semiconductor device includes forming a first level, forming a first barrier layer over the first level, forming a dielectric layer over the first barrier layer, forming an opening having side surfaces through the dielectric layer, etching the first barrier layer, and filling the opening with metal to form a first metal feature. The process also includes the step of replacing hydroxyl terminated ions on the side surfaces. This step of replacing the hydroxyl terminated ions can occur after the opening is formed or after the first barrier layer is etched. A semiconductor device produced by the method of manufacturing is also disclosed.Type: GrantFiled: January 31, 2002Date of Patent: March 30, 2004Assignee: Advanced Micro Devices, Inc.Inventors: Suzette K. Pangrle, Ecran Adem, Calvin Gabriel, Lynne A. Okada
-
Patent number: 6211087Abstract: A primary layer deposited over a secondary layer is planarized. A chemical mechanical polishing process is performed using a slurry which targets the primary layer. Then, chemical etching is performed using a chemical wet etchant which targets the secondary layer. The method is used, for example, when making connections to a lower layer through an insulating layer. Plug holes are formed through the insulating layer to the lower layer. Then the secondary layer is deposited. The secondary layer acts as a barrier layer or a glue layer.Type: GrantFiled: June 29, 1998Date of Patent: April 3, 2001Assignee: VLSI Technology, Inc.Inventors: Calvin Gabriel, Milind Weling
-
Patent number: 6080677Abstract: An isolation structure on an integrated circuit is formed using a shallow trench isolation process. A layer of buffer oxide is formed on a substrate. A layer of nitride is formed on the layer of buffer oxide. The layer of nitride and the layer of buffer oxide are patterned to form a trench area. The substrate including the trench area is subjected to a plasma comprising H.sub.2 O vapor, and a gaseous fluorocarbon or a fluorinated hydrocarbon gas to clean impurities on the trench area. The substrate is etched to form a trench within the trench area.Type: GrantFiled: December 30, 1997Date of Patent: June 27, 2000Assignee: VLSI Technology, Inc.Inventors: Calvin Gabriel, Ian Robert Harvey, Linda Leard
-
Patent number: 6060376Abstract: A gate region of a transistor is prepared for receiving a deposit of metal. A chemical mechanical polishing process is performed to reduce thickness of an insulation layer above the gate region. At the end of the chemical mechanical polishing process, a portion of the insulating layer remains above the gate region. An etch process is performed to remove the portion of the insulating layer remaining above the gate region. The etch process also removes a portion of polysilicon within the gate region and removes a top portion of spacers on either side of the gate region. A polysilicon selective etch-back is performed to remove an additional portion of the polysilicon within the gate region.Type: GrantFiled: January 12, 1998Date of Patent: May 9, 2000Assignee: VLSI Technology, Inc.Inventors: Calvin Gabriel, Xi-Wei Lin, Tammy Zheng, Linda Leard, Ian Robert Harvey
-
Patent number: 6022265Abstract: A complementary conditioning system for use in chemical mechanical polishing (CMP). The present invention functions with a CMP machine adapted for polishing a semiconductor wafer having tungsten components fabricated thereon. A polishing pad is mounted on the CMP machine. The polishing pad has a polishing surface configured for polishing the semiconductor wafer and its tungsten components. The performance of the polishing surface is characterized by a polishing efficiency. A complementary end-effector is mounted on the CMP machine. The complementary end-effector is adapted to chemically complement the tungsten components on the semiconductor wafer. The complementary end-effector is further adapted to contact the polishing surface and improve the polishing efficiency by chemically enhancing the polishing surface, thereby obtaining a more efficient removal rate for the chemical mechanical polishing.Type: GrantFiled: June 19, 1998Date of Patent: February 8, 2000Assignee: VLSI Technology, Inc.Inventors: Charles F. Drill, Calvin Gabriel, Milind Weling, Richard Russ, David E. Henderson
-
Patent number: 5730834Abstract: Forming tungsten plugs allows for a conformal step coverage into contacts in semiconductor wafer processing. By rinsing the wafers after the tungsten etchback but before the wafers have a chance to enter an oxygen-containing environment, the amount of fluorine-containing residue removed from the wafer can be increased. In this way, the connection between the tungsten plugs and a metallization layer can be improved.Type: GrantFiled: March 29, 1996Date of Patent: March 24, 1998Assignee: VLSI Technology, Inc.Inventor: Calvin Gabriel