Abstract: A system including a non-bus mastering target device that is equipped to request a bus master device to initiate a bus transaction, such as for example, a direct memory access by the target device. By providing the remote target device with the ability to request a bus master to initiate a transaction, overall system performance may be improved without requiring that the target device include unnecessary and expensive bus mastering logic.

Abstract: An Ethernet switch which includes a plurality of medium access control (MAC) interface logic circuits each coupled to an associated output port operative to perform serial-to-parallel conversion for frames being received from an associated output port and parallel-to-serial conversion for frames being transferred to an associated output port and other interfacing functions. The switch has an internal bus, a buffer memory coupled to each of the MAC interface logic circuits at one end and to the internal bus at another end, a switch central processor coupled to the internal bus and a multi-channel Direct Memory Access (DMA) Controller coupled to the internal bus and to the switch central processor, operative to transfer incoming frames to an external memory and to transfer frames stored temporarily in external memory to their destination in accordance with instructions from the switch central processor. An external memory controller is coupled to the DMA Controller and to an external memory port.