Abstract: A security door system for use with an existing building having an existing door. The security door system including a first secure wall and a first security door disposed in the first secure wall. The security door system also including a second secure wall extending from the first secure wall to the existing building and a third secure wall extending from the first secure wall to the existing building. The security door system further including a secure top supported by the first, second and third secure walls to create a first secure area. A method of monitoring and controlling who has access to an existing building. The method includes installing the security door system for the existing building to permit only authorized individuals to enter and permitting access of the authorized individuals to the existing building via the security door system.

Abstract: A system, method, and computer readable medium with instructions for verifying an original layout are disclosed. The original layout includes cells arranged in a cell hierarchy, front-end-of-line (FEOL) layers, and back-end-of-line (BEOL) layers. In one embodiment, a reduced layout is generated by trimming out cells below a top tier of the cell hierarchy and filtering out the FEOL layers. A text-based short check is executed on the reduced layout. Next, an augmented reduced layout is generated. The augmented reduced layout includes pin information for cells in a second tier connected to the top tier. An interconnectivity check is then executed on the augmented reduced layout based on a schematic for the circuit. Afterwards, a result (e.g., location of short or connectivity mismatch) based on at least one of the text-based short check and the interconnectivity check is outputted. A conventional LVS check may then be executed.

Abstract: Disclosed are processes for preparing dry or powder dairy compositions having low lactose contents and containing polyphenol compounds. The resultant dry or powder dairy compositions can be used to form reconstituted fluid dairy products, which can have improved organoleptic properties, such as less cooked flavor, sulfur odor, and brown color.

Abstract: A system, method, and computer readable medium with instructions for verifying an original layout are disclosed. The original layout includes cells arranged in a cell hierarchy, front-end-of-line (FEOL) layers, and back-end-of-line (BEOL) layers. In one embodiment, a reduced layout is generated by trimming out cells below a top tier of the cell hierarchy and filtering out the FEOL layers. A text-based short check is executed on the reduced layout. Next, an augmented reduced layout is generated. The augmented reduced layout includes pin information for cells in a second tier connected to the top tier. An interconnectivity check is then executed on the augmented reduced layout based on a schematic for the circuit. Afterwards, a result (e.g., location of short or connectivity mismatch) based on at least one of the text-based short check and the interconnectivity check is outputted. A conventional LVS check may then be executed.

Abstract: Disclosed are processes for preparing dry or powder dairy compositions having low lactose contents and containing polyphenol compounds. The resultant dry or powder dairy compositions can be used to form reconstituted fluid dairy products, which can have improved organoleptic properties, such as less cooked flavor, sulfur odor, and brown color.

Abstract: Disclosed are processes for reducing the cooked flavor, sulfur odor, and brown color of milk products that have been subjected to ultra-high temperature (UHT) sterilization via the UHT sterilization of certain milk fractions separately.

Abstract: Disclosed are processes for preparing dry or powder dairy compositions having low lactose contents and containing polyphenol compounds. The resultant dry or powder dairy compositions can be used to form reconstituted fluid dairy products, which can have improved organoleptic properties, such as less cooked flavor, sulfur odor, and brown color.

Abstract: Disclosed are processes for preparing dry or powder dairy compositions having low lactose contents and containing polyphenol compounds. The resultant dry or powder dairy compositions can be used to form reconstituted fluid dairy products, which can have improved organoleptic properties, such as less cooked flavor, sulfur odor, and brown color.

Abstract: Disclosed are processes for reducing the cooked flavor, sulfur odor, and brown color of milk products that have been subjected to ultra-high temperature (UHT) sterilization via the UHT sterilization of certain milk fractions separately.

Abstract: This disclosure is related to an apparatus for automatically separating spent drilling materials from air drilling operations. The apparatus includes a reservoir, a spent materials inlet, and a drill cuttings outlet. The apparatus also includes either a float system or a load cell system to actuate the drill cuttings outlet when the spent drilling materials reach a predetermined amount in the reservoir.

Abstract: This disclosure is related to an apparatus for automatically separating spent drilling materials from air drilling operations. The apparatus includes a reservoir, a spent materials inlet, and a drill cuttings outlet. The apparatus also includes either a float system or a load cell system to actuate the drill cuttings outlet when the spent drilling materials reach a predetermined amount in the reservoir.

Abstract: A layout versus schematic (LVS) comparison tool determines one-to-one equivalency between an integrated circuit schematic and an integrated circuit layout by performing operations to color a schematic graph of a parent cell to an equilibrium state. An operation is then performed to recolor nets connected to first and second child cells having the same device value within the parent cell, using a net coloring operation that recolors a first plurality of symmetric pins of the first child cell and recolors a second plurality of symmetric pins of the second child cell. Distinct device values are then generated for the first and second child cells by determining a first product of the colors of the recolored first plurality of symmetric pins and a second product of the colors of the recolored second plurality of symmetric pins.

Abstract: A system, comprising a receiving module to receive a request to load a component, a stack to record the request and a loader to fulfill the request, wherein when the request has been fulfilled the request is removed from the stack and when the loading of the component is unsuccessful, contents of the stack are made available to a user to indicate the unsuccessfully loaded component.

Abstract: A system, comprising a plug-in data structure to store plug-in data, the plug-in data structure including an initial list and an end list and a plug-in manager to read the plug-in data structure and start plug-ins corresponding to an order in the plug-in data structure, wherein the plug-in manager starts plug-ins on the initial list prior to plug-ins on the end list.

Abstract: A layout versus schematic (LVS) comparison tool determines one-to-one equivalency between an integrated circuit schematic and an integrated circuit layout by performing operations to color a schematic graph of a parent cell to an equilibrium state. An operation is then performed to recolor nets connected to first and second child cells having the same device value within the parent cell, using a net coloring operation that recolors a first plurality of symmetric pins of the first child cell and recolors a second plurality of symmetric pins of the second child cell. Distinct device values are then generated for the first and second child cells by determining a first product of the colors of the recolored first plurality of symmetric pins and a second product of the colors of the recolored second plurality of symmetric pins.

Abstract: A logger system, comprising a core component configured to receive a log statement from an application program, the log statement including a group identifier and a level identifier, the core component further configured to direct a log report generated from the log statement to an output stream based on the group identifier and the level identifier of the log statement and log controls accessible to the core component.

Abstract: A system, comprising a stream source class loader retrieving streaming data to create a desired class object, an interface coupled to the stream source class loader and a plurality of streaming sources containing information including the location of data, wherein requests for data are communicated from the stream source class loader to the streaming sources via the interface and, data passes from the stream sources to the stream source class loader via the interface, the streaming sources searching the data locations for the requested data.

Abstract: A system, comprising a receiving module to receive a request to load a component, a stack to record the request and a loader to fulfill the request, wherein when the request has been fulfilled the request is removed from the stack and when the loading of the component is unsuccessful, contents of the stack are made available to a user to indicate the unsuccessfully loaded component.

Abstract: A layout versus schematic (LVS) comparison tool performs layout versus schematic comparison of integrated circuits having memory cells and non-memory cells therein. These operations are particularly useful when the integrated circuit layout includes one or more arrays of memory cells (i.e., bit cells) that are identified at a transistor level in the layout netlist. Such operations include scanning a layout netlist of the integrated circuit at the transistor level to identify a first device therein that has an identifiable characteristic associated with the plurality of memory cells relative to the plurality of non-memory cells. Upon detection of the identifiable characteristic, the layout netlist of a first memory cell containing the first device is traced in order to identify a first bit line and/or a first word line therein that is electrically coupled to the first memory cell.

Abstract: A layout versus schematic (LVS) comparison tool determines one-to-one equivalency between an integrated circuit schematic and an integrated circuit layout by performing operations to color a schematic graph of a parent cell to an equilibrium state. An operation is then performed to recolor nets connected to first and second child cells having the same device value within the parent cell, using a net coloring operation that recolors a first plurality of symmetric pins of the first child cell and recolors a second plurality of symmetric pins of the second child cell. Distinct device values are then generated for the first and second child cells by determining a first product of the colors of the recolored first plurality of symmetric pins and a second product of the colors of the recolored second plurality of symmetric pins.