Abstract: A system and method of verifying the format of a simulated signal produced during the simulation of an electronic circuit is disclosed. One aspect of the present invention includes a method of extracting timing information from a single simulated serial digital audio signal that comprises both data and clock. An embodiment of the present invention may verify operation of the simulated electronic circuit by setting the value of a first simulated signal according to predetermined events that occur in a second simulated signal. The second simulated signal may be parsed using timing information extracted from the second simulated signal, and the format of the second simulated signal may be matched against a predetermined format based upon the results of the parsing.