Abstract: Components in a system-on-chip (SOC) may communicate through a mesh interconnect. Such components include processing circuits that may initiate memory transactions and memory circuits that may be access but memory transactions. The SOC also includes access circuits to control memory transactions directed to memory circuits through their component interfaces. The access circuits may receive memory transactions and generate indications of whether a processing circuit that initiated the memory transaction has authority to access a region of memory in the memory circuit according to the memory transaction. In some examples, execution of memory transactions may proceed according to the generated indications. In some examples, a desired access (e.g., reading, writing, executing) to a targeted memory address may be indicated by an instruction in the memory transaction.

Abstract: Dynamically adjusting memory allocations based on Quality-of-Service (QoS) pool threshold values in processor-based devices is disclosed herein. In one exemplary embodiment, a processor-based device provides a storage controller circuit communicatively coupled to a memory device. The storage controller circuit comprises a dedicated storage device and a plurality of pool threshold values corresponding to a plurality of pools, wherein each pool corresponds to one or more QoS levels, and each pool threshold value defines an allocation of the dedicated storage device for the corresponding pool. For each pool of the plurality of pools, the storage controller circuit collects a usage statistic during a sampling period, and determines, based on the usage statistic, whether to modify the pool threshold value corresponding to the pool.