Patents by Inventor Cameron MCKNIGHT-MACNEIL

Cameron MCKNIGHT-MACNEIL has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9824949
    Abstract: Packaging solutions for devices and systems comprising lateral GaN power transistors are disclosed, including components of a packaging assembly, a semiconductor device structure, and a method of fabrication thereof. In the packaging assembly, a GaN die, comprising one or more lateral GaN power transistors, is sandwiched between first and second leadframe layers, and interconnected using low inductance interconnections, without wirebonding. For thermal dissipation, the dual leadframe package assembly can be configured for either front-side or back-side cooling. Preferred embodiments facilitate alignment and registration of high current/low inductance interconnects for lateral GaN devices, in which contact areas or pads for source, drain and gate contacts are provided on the front-side of the GaN die.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: November 21, 2017
    Assignee: GaN Systems Inc.
    Inventors: Cameron McKnight-MacNeil, Greg P. Klowak, Ahmad Mizan, Stephen Coates
  • Patent number: 9818692
    Abstract: Devices and systems comprising high current/high voltage GaN semiconductor devices are disclosed. A GaN die, comprising a lateral GaN transistor, is sandwiched between an overlying header and an underlying composite thermal dielectric layer. Fabrication comprises providing a conventional GaN device structure fabricated on a low cost silicon substrate (GaN-on-Si die), mechanically and electrically attaching source, drain and gate contact pads of the GaN-on-Si die to corresponding contact areas of conductive tracks of the header, then entirely removing the silicon substrate. The exposed substrate-surface of the epi-layer stack is coated with the composite dielectric thermal layer. Preferably, the header comprises a ceramic dielectric support layer having a CTE matched to the GaN epi-layer stack. The thermal dielectric layer comprises a high dielectric strength thermoplastic polymer and a dielectric filler having a high thermal conductivity.
    Type: Grant
    Filed: March 23, 2016
    Date of Patent: November 14, 2017
    Assignee: GaN Systems Inc.
    Inventors: John Roberts, Greg P. Klowak, Cameron McKnight-MacNeil
  • Patent number: 9818857
    Abstract: A fault tolerant design for large area nitride semiconductor devices is provided, which facilitates testing and isolation of defective areas. A transistor comprises an array of a plurality of islands, each island comprising an active region, source and drain electrodes, and a gate electrode. Electrodes of each island are electrically isolated from electrodes of neighboring islands in at least one direction of the array. Source, drain and gate contact pads are provided to enable electrical testing of each island. After electrical testing of islands to identify defective islands, overlying electrical connections are formed to interconnect source electrodes in parallel, drain electrodes in parallel, and to interconnect gate electrodes to form a common gate electrode of large gate width Wg. Interconnections are provided selectively to good islands, while electrically isolating defective islands. This approach makes it economically feasible to fabricate large area GaN devices, including hybrid devices.
    Type: Grant
    Filed: October 28, 2014
    Date of Patent: November 14, 2017
    Assignee: GaN Systems Inc.
    Inventors: Greg P. Klowak, Cameron McKnight-Macneil, Howard Tweddle, Ahmad Mizan, Nigel Springett
  • Patent number: 9589869
    Abstract: Packaging solutions for devices and systems comprising lateral GaN power transistors are disclosed, including components of a packaging assembly, a semiconductor device structure, and a method of fabrication thereof. In the packaging assembly, a GaN die, comprising one or more lateral GaN power transistors, is sandwiched between first and second leadframe layers, and interconnected using low inductance interconnections, without wirebonding. For thermal dissipation, the dual leadframe package assembly can be configured for either front-side or back-side cooling. Preferred embodiments facilitate alignment and registration of high current/low inductance interconnects for lateral GaN devices, in which contact areas or pads for source, drain and gate contacts are provided on the front-side of the GaN die.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: March 7, 2017
    Assignee: GaN Systems Inc.
    Inventors: Cameron McKnight-MacNeil, Greg P. Klowak, Ahmad Mizan
  • Patent number: 9589868
    Abstract: Packaging solutions for large area, GaN die comprising one or more lateral GaN power transistor devices and systems are disclosed. Packaging assemblies comprise an interposer sub-assembly comprising the lateral GaN die and a leadframe. The GaN die is electrically connected to the leadframe using bump or post interconnections, silver sintering, or other low inductance interconnections. Then, attachment of the GaN die to the substrate and the electrical connections of the leadframe to contacts on the substrate are made in a single process step. The sub-assembly may be mounted in a standard power module, or alternatively on a substrate, such as a printed circuit board. For high current applications, the sub-assembly also comprises a ceramic substrate for heat dissipation. This packaging scheme provides interconnections with lower inductance and higher current capacity, simplifies fabrication, and enables improved thermal matching of components, compared with conventional wirebonded power modules.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: March 7, 2017
    Assignee: GaN Systems Inc.
    Inventors: Cameron McKnight-MacNeil, Greg P. Klowak, Ahmad Mizan
  • Publication number: 20160380090
    Abstract: Devices and systems comprising high current/high voltage GaN semiconductor devices are disclosed. A GaN die, comprising a lateral GaN transistor, is sandwiched between an overlying header and an underlying composite thermal dielectric layer. Fabrication comprises providing a conventional GaN device structure fabricated on a low cost silicon substrate (GaN-on-Si die), mechanically and electrically attaching source, drain and gate contact pads of the GaN-on-Si die to corresponding contact areas of conductive tracks of the header, then entirely removing the silicon substrate. The exposed substrate-surface of the epi-layer stack is coated with the composite dielectric thermal layer. Preferably, the header comprises a ceramic dielectric support layer having a CTE matched to the GaN epi-layer stack. The thermal dielectric layer comprises a high dielectric strength thermoplastic polymer and a dielectric filler having a high thermal conductivity.
    Type: Application
    Filed: March 23, 2016
    Publication date: December 29, 2016
    Inventors: John ROBERTS, Greg P. KLOWAK, Cameron MCKNIGHT-MACNEIL
  • Publication number: 20160307826
    Abstract: Packaging solutions for devices and systems comprising lateral GaN power transistors are disclosed, including components of a packaging assembly, a semiconductor device structure, and a method of fabrication thereof. In the packaging assembly, a GaN die, comprising one or more lateral GaN power transistors, is sandwiched between first and second leadframe layers, and interconnected using low inductance interconnections, without wirebonding. For thermal dissipation, the dual leadframe package assembly can be configured for either front-side or back-side cooling. Preferred embodiments facilitate alignment and registration of high current/low inductance interconnects for lateral GaN devices, in which contact areas or pads for source, drain and gate contacts are provided on the front-side of the GaN die.
    Type: Application
    Filed: June 30, 2016
    Publication date: October 20, 2016
    Inventors: Cameron MCKNIGHT-MACNEIL, Greg P. KLOWAK, Ahmad MIZAN, Stephen COATES
  • Publication number: 20160284829
    Abstract: A fault tolerant design for large area nitride semiconductor devices is provided, which facilitates testing and isolation of defective areas. A transistor comprises an array of a plurality of islands, each island comprising an active region, source and drain electrodes, and a gate electrode. Electrodes of each island are electrically isolated from electrodes of neighbouring islands in at least one direction of the array. Source, drain and gate contact pads are provided to enable electrical testing of each island. After electrical testing of islands to identify defective islands, overlying electrical connections are formed to interconnect source electrodes in parallel, drain electrodes in parallel, and to interconnect gate electrodes to form a common gate electrode of large gate width Wg. Interconnections are provided selectively to good islands, while electrically isolating defective islands. This approach makes it economically feasible to fabricate large area GaN devices, including hybrid devices.
    Type: Application
    Filed: October 28, 2014
    Publication date: September 29, 2016
    Inventors: Greg P. KLOWAK, Cameron MCKNIGHT-MACNEIL, Howard TWEDDLE, Ahmad MIZAN, Nigel SPRINGETT
  • Publication number: 20160268185
    Abstract: Packaging solutions for devices and systems comprising lateral GaN power transistors are disclosed, including components of a packaging assembly, a semiconductor device structure, and a method of fabrication thereof In the packaging assembly, a GaN die, comprising one or more lateral GaN power transistors, is sandwiched between first and second leadframe layers, and interconnected using low inductance interconnections, without wirebonding. For thermal dissipation, the dual leadframe package assembly can be configured for either front-side or back-side cooling. Preferred embodiments facilitate alignment and registration of high current/low inductance interconnects for lateral GaN devices, in which contact areas or pads for source, drain and gate contacts are provided on the front-side of the GaN die.
    Type: Application
    Filed: March 9, 2016
    Publication date: September 15, 2016
    Inventors: Cameron MCKNIGHT-MACNEIL, Greg P. KLOWAK, Ahmad MIZAN
  • Publication number: 20160268190
    Abstract: Packaging solutions for large area, GaN die comprising one or more lateral GaN power transistor devices and systems are disclosed. Packaging assemblies comprise an interposer sub-assembly comprising the lateral GaN die and a leadframe. The GaN die is electrically connected to the leadframe using bump or post interconnections, silver sintering, or other low inductance interconnections. Then, attachment of the GaN die to the substrate and the electrical connections of the leadframe to contacts on the substrate are made in a single process step. The sub-assembly may be mounted in a standard power module, or alternatively on a substrate, such as a printed circuit board. For high current applications, the sub-assembly also comprises a ceramic substrate for heat dissipation. This packaging scheme provides interconnections with lower inductance and higher current capacity, simplifies fabrication, and enables improved thermal matching of components, compared with conventional wirebonded power modules.
    Type: Application
    Filed: March 9, 2016
    Publication date: September 15, 2016
    Inventors: Cameron MCKNIGHT-MACNEIL, Greg P. KLOWAK, Ahmad MIZAN
  • Patent number: 9153509
    Abstract: A fault tolerant design for large area nitride semiconductor devices is provided, which facilitates testing and isolation of defective areas. A transistor comprises an array of a plurality of islands, each island comprising an active region, source and drain electrodes, and a gate electrode. Electrodes of each island are electrically isolated from electrodes of neighboring islands in at least one direction of the array. Source, drain and gate contact pads are provided to enable electrical testing of each island. After electrical testing of islands to identify defective islands, overlying electrical connections are formed to interconnect source electrodes in parallel, drain electrodes in parallel, and to interconnect gate electrodes to form a common gate electrode of large gate width Wg. Interconnections are provided selectively to good islands, while electrically isolating defective islands. This approach makes it economically feasible to fabricate large area GaN devices, including hybrid devices.
    Type: Grant
    Filed: December 12, 2014
    Date of Patent: October 6, 2015
    Assignee: GaN Systems Inc.
    Inventors: Gregory P. Klowak, Cameron McKnight-MacNeil, Howard Tweddle, Ahmad Mizan, Nigel Springett
  • Publication number: 20150162252
    Abstract: A fault tolerant design for large area nitride semiconductor devices is provided, which facilitates testing and isolation of defective areas. A transistor comprises an array of a plurality of islands, each island comprising an active region, source and drain electrodes, and a gate electrode. Electrodes of each island are electrically isolated from electrodes of neighboring islands in at least one direction of the array. Source, drain and gate contact pads are provided to enable electrical testing of each island. After electrical testing of islands to identify defective islands, overlying electrical connections are formed to interconnect source electrodes in parallel, drain electrodes in parallel, and to interconnect gate electrodes to form a common gate electrode of large gate width Wg. Interconnections are provided selectively to good islands, while electrically isolating defective islands. This approach makes it economically feasible to fabricate large area GaN devices, including hybrid devices.
    Type: Application
    Filed: December 12, 2014
    Publication date: June 11, 2015
    Applicant: GAN SYSTEMS INC.
    Inventors: Gregory P. KLOWAK, Cameron MCKNIGHT-MACNEIL, Howard TWEDDLE, Ahmad MIZAN, Nigel SPRINGETT