Patents by Inventor Cameron R. McClintock
Cameron R. McClintock has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9094014Abstract: In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base signal routing architecture to the IP function block.Type: GrantFiled: April 2, 2014Date of Patent: July 28, 2015Assignee: Altera CorporationInventors: Andy L. Lee, Cameron R. McClintock, Brian D. Johnson, Richard G. Cliff, Srinivas T. Reddy, Christopher F. Lane, Paul Leventis, Vaughn Betz, David Lewis
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Publication number: 20140210515Abstract: In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base signal routing architecture to the IP function block.Type: ApplicationFiled: April 2, 2014Publication date: July 31, 2014Applicant: Altera CorporationInventors: Andy L. Lee, Cameron R. McClintock, Brian D. Johnson, Richard G. Cliff, Srinivas T. Reddy, Christopher F. Lane, Paul Leventis, Vaughn Betz, David Lewis
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Patent number: 8732646Abstract: In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base signal routing architecture to the IP function block.Type: GrantFiled: March 20, 2013Date of Patent: May 20, 2014Assignee: Altera CorporationInventors: Andy L. Lee, Cameron R. McClintock, Brian D. Johnson, Richard G. Cliff, Srinivas T. Reddy, Christopher F. Lane, Paul Leventis, Vaughn Betz, David Lewis
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Patent number: 8198914Abstract: A programmable logic device (PLD) includes at least two regions. Each region includes electrical circuitry that has a set of transistors. Each of the two regions has a corresponding fixed transistor threshold voltage, a corresponding fixed transistor body bias, and a corresponding fixed supply voltage.Type: GrantFiled: April 30, 2011Date of Patent: June 12, 2012Assignee: Altera CorporationInventors: Andy L. Lee, Christopher F. Lane, Ketan H. Zaveri, Richard G. Cliff, Cameron R. McClintock, Srinivas T. Reddy, David Lewis
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Publication number: 20110204919Abstract: A programmable logic device (PLD) includes at least two regions. Each region includes electrical circuitry that has a set of transistors. Each of the two regions has a corresponding fixed transistor threshold voltage, a corresponding fixed transistor body bias, and a corresponding fixed supply voltage.Type: ApplicationFiled: April 30, 2011Publication date: August 25, 2011Inventors: Andy L. Lee, Christopher F. Lane, Ketan H. Zaveri, Richard G. Cliff, Cameron R. McClintock, Srinivas T. Reddy, David Lewis
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Patent number: 7936184Abstract: A programmable logic device (PLD) includes at least two regions. Each region includes electrical circuitry that has a set of transistors. Each of the two regions has a corresponding fixed transistor threshold voltage, a corresponding fixed transistor body bias, and a corresponding fixed supply voltage.Type: GrantFiled: February 24, 2006Date of Patent: May 3, 2011Assignee: Altera CorporationInventors: Andy L. Lee, Christopher F. Lane, Ketan H. Zaveri, Richard G. Cliff, Cameron R. McClintock, Srinivas T. Reddy, David Lewis
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Patent number: 6970014Abstract: An embodiment of this invention pertains to a 3-sided routing architecture to interconnect function blocks, such as logic array blocks (“LABs”), within a programmable logic device (“PLD”). In the 3-sided routing architecture, inputs and outputs on a first side of a function block connect to a first channel, and inputs and outputs on a second side of the function block connect to a second channel where the second side is opposite the first side. Inputs and outputs on a third side of the function block connect to a third channel. A fourth channel associated with a fourth side of the function block, the fourth side opposite the third side, is coupled only to the first channel and the second channel. In one configuration, the inputs and outputs on each of the first side, the second side, and the third side have an equal number of inputs and outputs. In this configuration, each of the first channel, the second channel, and the third channel have the same width.Type: GrantFiled: July 21, 2003Date of Patent: November 29, 2005Assignee: Altera CorporationInventors: David M. Lewis, Paul Leventis, Andy L. Lee, Brian D. Johnson, Richard Cliff, Srinivas T. Reddy, Christopher F. Lane, Cameron R. McClintock, Vaughn Betz, Chris Wysocki, Alexander R. Marquardt
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Patent number: 6897678Abstract: A programmable logic device is provided that contains circuitry that may be used for observing logic signals from programmable logic circuits on the device for testing the operation of the device. Circuitry is also provided that may be used for preloading data into various circuits on the device. The logic signal observing circuitry may allow registered signals to be observed, may allow combinatorial signals to be observed, or may allow both registered and combinatorial signals to be observed.Type: GrantFiled: September 25, 2002Date of Patent: May 24, 2005Assignee: Altera CorporationInventors: Ketan Zaveri, Christopher F. Lane, Srinivas T. Reddy, Andy L. Lee, Cameron R. McClintock, Bruce B. Pedersen
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Patent number: 6895570Abstract: An embodiment of this invention pertains to a wire that interconnects multiple function blocks within a programmable logic device (“PLD”). An electrically optimum physical length is determined for the wire. A wire having the electrically optimum physical length transmits a signal down the wire as fast as possible. Some of the wires used in the PLD have a physical length substantially the same as the electrically optimum physical length or an adjustment of the electrically optimum physical length to account for non-electrical considerations. The physical length, as used herein, is the measured length of the wire. A logical length of the wire, as used herein, is the number of function blocks that the wire spans. Given that the function blocks have a different height and width, the logical length of the wire varies depending on the orientation of the wire. A routing architecture is an array that includes rows and columns of function blocks.Type: GrantFiled: January 25, 2002Date of Patent: May 17, 2005Assignee: Altera CorporationInventors: David M. Lewis, Vaughn Betz, Paul Leventis, Michael Chan, Cameron R. McClintock, Andy L. Lee, Christopher F. Lane, Srinivas T. Reddy, Richard Cliff
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Patent number: 6630842Abstract: An embodiment of this invention pertains to a 3-sided routing architecture to interconnect function blocks, such as logic array blocks (“LABs”), within a programmable logic device (“PLD”). In the 3-sided routing architecture, inputs and outputs on a first side of a function block connect to a first channel, and inputs and outputs on a second side of the function block connect to a second channel where the second side is opposite the first side. Inputs and outputs on a third side of the function block connect to a third channel. A fourth channel associated with a fourth side of the function block, the fourth side opposite the third side, is coupled only to the first channel and the second channel. In one configuration, the inputs and outputs on each of the first side, the second side, and the third side have an equal number of inputs and outputs. In this configuration, each of the first channel, the second channel, and the third channel have the same width.Type: GrantFiled: May 6, 2002Date of Patent: October 7, 2003Assignee: Altera CorporationInventors: David M. Lewis, Paul Leventis, Andy L. Lee, Brian D. Johnson, Richard Cliff, Srinivas T. Reddy, Christopher F. Lane, Cameron R. McClintock, Vaughn Betz, Chris Wysocki, Alexander R. Marquardt
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Publication number: 20030033584Abstract: A programmable logic device is provided that contains circuitry that may be used for observing logic signals from programmable logic circuits on the device for testing the operation of the device. Circuitry is also provided that may be used for preloading data into various circuits on the device. The logic signal observing circuitry may allow registered signals to be observed, may allow combinatorial signals to be observed, or may allow both registered and combinatorial signals to be observed.Type: ApplicationFiled: September 25, 2002Publication date: February 13, 2003Applicant: Altera CorporationInventors: Ketan Zaveri, Christopher F. Lane, Srinivas T. Reddy, Andy L. Lee, Cameron R. McClintock, Bruce B. Pedersen
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Patent number: 6481000Abstract: A programmable logic device is provided that contains circuitry that may be used for observing logic signals from programmable logic circuits on the device for testing the operation of the device. Circuitry is also provided that may be used for preloading data into various circuits on the device. The logic signal observing circuitry may allow registered signals to be observed, may allow combinatorial signals to be observed, or may allow both registered and combinatorial signals to be observed.Type: GrantFiled: June 29, 2000Date of Patent: November 12, 2002Assignee: Altera CorporationInventors: Ketan Zaveri, Christopher F. Lane, Srinivas T. Reddy, Andy L. Lee, Cameron R. McClintock, Bruce B. Pedersen
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Publication number: 20020166106Abstract: An embodiment of this invention pertains to a wire that interconnects multiple function blocks within a programmable logic device (“PLD”). An electrically optimum physical length is determined for the wire. A wire having the electrically optimum physical length transmits a signal down the wire as fast as possible. Some of the wires used in the PLD have a physical length substantially the same as the electrically optimum physical length or an adjustment of the electrically optimum physical length to account for non-electrical considerations. The physical length, as used herein, is the measured length of the wire. A logical length of the wire, as used herein, is the number of function blocks that the wire spans. Given that the function blocks have a different height and width, the logical length of the wire varies depending on the orientation of the wire.Type: ApplicationFiled: January 25, 2002Publication date: November 7, 2002Inventors: David M. Lewis, Vaughn Betz, Paul Leventis, Michael Chan, Cameron R. McClintock, Andy L. Lee, Christopher F. Lane, Srinivas T. Reddy, Richard Cliff
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Patent number: 6335634Abstract: Programmable interconnection group arrangements for selectively interconnecting logic on a programmable logic device are provided. Interconnection groups may be programmed to route signals between the various conductors on the device, and to route signals from various logic regions on the device to the various conductors. The interconnection groups provide routing flexibility and efficiency without using excessive amounts of interconnection resources.Type: GrantFiled: May 22, 2000Date of Patent: January 1, 2002Inventors: Srinivas T. Reddy, Ketan Zaveri, Christopher F. Lane, Andy L. Lee, Cameron R. McClintock, Bruce B. Pedersen, Manuel Mejia, Richard G. Cliff
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Patent number: 6157210Abstract: A programmable logic device is provided that contains circuitry that may be used for observing logic signals from programmable logic circuits on the device for testing the operation of the device. Circuitry is also provided that may be used for preloading data into various circuits on the device. The logic signal observing circuitry may allow registered signals to be observed, may allow combinatorial signals to be observed, or may allow both registered and combinatorial signals to be observed.Type: GrantFiled: May 21, 1998Date of Patent: December 5, 2000Assignee: Altera CorporationInventors: Ketan Zaveri, Christopher F. Lane, Srinivas T. Reddy, Andy L. Lee, Cameron R. McClintock, Bruce B. Pedersen
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Patent number: 6134173Abstract: A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.Type: GrantFiled: November 2, 1998Date of Patent: October 17, 2000Assignee: Altera CorporationInventors: Richard G. Cliff, L. Todd Cope, Cameron R. McClintock, William Leong, James A. Watson, Joseph Huang, Bahram Ahanin
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Patent number: 6107824Abstract: Programmable interconnection group arrangements for selectively interconnecting logic on a programmable logic device are provided. Interconnection groups may be programmed to route signals between the various conductors on the device, and to route signals from various logic regions on the device to the various conductors. The interconnection groups provide routing flexibility and efficiency without using excessive amounts of interconnection resources.Type: GrantFiled: May 28, 1998Date of Patent: August 22, 2000Assignee: Altera CorporationInventors: Srinivas T. Reddy, Ketan Zaveri, Christopher F. Lane, Andy L. Lee, Cameron R. McClintock, Bruce B. Pedersen, Manuel Mejia, Richard G. Cliff
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Patent number: 6023439Abstract: A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.Type: GrantFiled: September 17, 1998Date of Patent: February 8, 2000Assignee: Altera CorporationInventors: Richard G. Cliff, L. Todd Cope, Cameron R. McClintock, William Leong, James A. Watson, Joseph Huang, Bahram Ahanin
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Patent number: 5883850Abstract: A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.Type: GrantFiled: June 18, 1996Date of Patent: March 16, 1999Assignee: Altera CorporationInventors: Fung Fung Lee, Richard G. Cliff, L. Todd Cope, Cameron R. McClintock, William Leong, James A. Watson, Joseph Huang, Bahram Ahanin
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Patent number: RE38651Abstract: A programmable variable depth and width random-access memory circuit is provided. The memory circuit contains rows and columns of memory cells for storing data. A row decoder is used to address individual rows of the memory cells. Column address circuitry receives a column address signal and a width and depth selection signal. A column decoder within the column address circuitry addresses one or more columns of memory cells of the RAM array based on the selected width of the array. The output of the column decoder is routed to the appropriate column or columns of memory cells by a pattern of fixed connections and a group of programmable multiplexers. The number of data output lines to which data signals are provided is determined by the selected width of the RAM array. The output circuitry contains a group of programmable demultiplexers and a routing array having a pattern of fixed connections suitable for passing data signals from the RAM array to the selected number of data output lines.Type: GrantFiled: June 12, 1998Date of Patent: November 9, 2004Assignee: Altera CorporationInventors: Chiakang Sung, Wanli Chang, Joseph Huang, Richard G. Cliff, L. Todd Cope, Cameron R. McClintock, William Leong, James A. Watson, Bahram Ahanin