Abstract: This invention concerns a quantum device, suitable for quantum computing, based on dopant atoms located in a solid semiconductor or insulator substrate. In further aspects the device is scaled up. The invention also concerns methods of reading out from the devices, initializing them, using them to perform logic operations and making them.

Abstract: The correction of errors in the transport and processing of qubits makes use of logical qubits made up of a plurality of physical qubits. The process takes place on a spatial array of physical qubit sites arranged with a quasi-2-dimensional topology having a first line of physical qubit sites and second line of physical qubit sites, where the first and second lines are arranged in parallel, with the sites of the first line in registration with corresponding sites in the second line. Between the first and second lines of physical qubit sites are a plurality of logic function gates, each comprised of a first physical qubit gate site associated with a first physical qubit site in the first line, and a second physical qubit gate site associated with the physical qubit site in the second line that corresponds to the first physical qubit site.

Abstract: This invention concerns a quantum device, suitable for quantum computing, based on dopant atoms located in a solid semiconductor or insulator substrate. In further aspects the device is scaled up. The invention also concerns methods of reading out from the devices, initializing them, using them to perform logic operations and making them.

Abstract: Ionisation of one of a pair of dopant atoms in a substrate creates a double well potential, and a charge qubit is realised by the location of one or more electrons or holes within this potential. The dopant atoms may comprise phosphorous atoms, located in a silicon substrate. A solid state quantum computer may be formed using a plurality of pairs of dopant atoms, corresponding gate electrodes, and read-out devices comprising single electron transistors.

Abstract: This invention concerns quantum error correction, that is the correction of errors in the transport and processing of qubits, by use of logical qubits made up of a plurality of physical qubits. The process takes place on a spatial array of physical qubit sites arranged with a quasi-2-dimensional topology having a first line of physical qubit sites and second line of physical qubit sites, where the first and second lines are arranged in parallel, with the sites of the first line in registration with corresponding sites in the second line. Between the first and second lines of physical qubit sites are a plurality of logic function gates, each comprised of a first physical qubit gate site associated with a first physical qubit site in the first line, and a second physical qubit gate site associated with the physical qubit site in the second line that corresponds to the first physical qubit site.

Abstract: Ionisation of one of a pair of dopant atoms (11, 12) in a substrate (13) creates a double well potential, and a charge qubit is realised by the location of one or more electrons or holes (14) within this potential. The dopant atoms may comprise phosphorous atoms, located in a silicon substrate. A solid state quantum computer may be formed using a plurality of pairs of dopant atoms (11, 12), corresponding gate electrodes (22, 23), and read-out devices comprising single electron transistors (24).