Patents by Inventor Can K. Que

Can K. Que has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • BOOSTING LOCAL MEMORY PERFORMANCE IN PROCESSOR GRAPHICS
    Publication number: 20200371804
    Abstract: In some cases, processor graphics with a slower local memory can compensate by using another memory in place of the lowest level or L3 cache. For example, in some processors, there is a large register space that can be used for the local memory function by allocating the local memory within those registers. Also, since the registers do not operate with barriers, barriers can be simulated by letting one execution unit thread execute more SIMD instructions. For example, one execution thread may simulate a whole work-group in the OpenCL API.
    Type: Application
    Filed: August 6, 2020
    Publication date: November 26, 2020
    Inventor: Can K. Que
  • Boosting local memory performance in processor graphics
    Patent number: 10768935
    Abstract: In some cases, processor graphics with a slower local memory can compensate by using another memory in place of the lowest level or L3 cache. For example, in some processors, there is a large register space that can be used for the local memory function by allocating the local memory within those registers. Also, since the registers do not operate with barriers, barriers can be simulated by letting one execution unit thread execute more SIMD instructions. For example, one execution thread may simulate a whole work-group in the OpenCL API.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: September 8, 2020
    Assignee: Intel Corporation
    Inventor: Can K. Que
  • BOOSTING LOCAL MEMORY PERFORMANCE IN PROCESSOR GRAPHICS
    Publication number: 20180300139
    Abstract: In some cases, processor graphics with a slower local memory can compensate by using another memory in place of the lowest level or L3 cache. For example, in some processors, there is a large register space that can be used for the local memory function by allocating the local memory within those registers. Also, since the registers do not operate with barriers, barriers can be simulated by letting one execution unit thread execute more SIMD instructions. For example, one execution thread may simulate a whole work-group in the OpenCL API.
    Type: Application
    Filed: October 29, 2015
    Publication date: October 18, 2018
    Inventor: Can K. Que