Abstract: The present invention provides a program counter compression method and a hardware circuit thereof. The compression method of the present invention includes the following steps: step (1), acquiring execution condition of instructions sent by a processor and classifying and screening said instructions based on said execution condition of the instructions; step (2), executing differential operation on instruction count values of the objective classification and the stall periods based on the classifying and screening result and splicing the obtained differential values; step (3), dictionary encoding the valid differential slicing data segments recorded in step (2). The present invention effectively combines the architecture compression and non-architecture compression and proposes a three-stage compression scheme by organizing and applying classifying and screening, differential encoding and dictionary compression, which drastically increases the compression ratio of the program counter.

Abstract: The present invention provides a program counter compression method and a hardware circuit thereof. The compression method of the present invention includes the following steps: step (1), acquiring execution condition of instructions sent by a processor and classifying and screening said instructions based on said execution condition of the instructions; step (2), executing differential operation on instruction count values of the objective classification and the stall periods based on the classifying and screening result and splicing the obtained differential values; step (3), dictionary encoding the valid differential slicing data segments recorded in step (2). The present invention effectively combines the architecture compression and non-architecture compression and proposes a three-stage compression scheme by organizing and applying classifying and screening, differential encoding and dictionary compression, which drastically increases the compression ratio of the program counter.