Abstract: Methods and systems for catheter navigation are provided. The method may include obtaining at least one real-time image associated with a subject, the at least one real-time image including a catheter at least partially inside the subject; determining spatial position information associated with the catheter based on the at least one real-time image; and directing a display device to configure a virtual object corresponding to the catheter in a reference image associated with the subject based on the spatial position information.

Abstract: An example manufacturing method includes performing first ion implantation into a first area of a substrate to form a buried layer. Second ion implantation into a second area of the substrate is performed to form a pre-dopant, where the second area is disposed around a periphery of the first area, and a thermal diffusion capability of ions in the pre-dopant is higher than a thermal diffusion capability of ions at the buried layer. An epitaxial layer is formed on a side, of the substrate, on which the buried layer and the pre-dopant are disposed. Third ion implantation into the epitaxial layer is performed, in correspondence to the second area, to form a deep well. Thermal annealing is performed to thermally diffuse ions at the buried layer, in the pre-dopant, and in the deep well.

Abstract: Methods and systems for catheter navigation are provided. The method may include obtaining at least one real-time image associated with a subject, the at least one real-time image including a catheter at least partially inside the subject; determining spatial position information associated with the catheter based on the at least one real-time image; and directing a display device to configure a virtual object corresponding to the catheter in a reference image associated with the subject based on the spatial position information.

Abstract: A variable capacitor includes a semiconductor substrate, a well region, and a gate electrode. The well region is disposed in the semiconductor substrate. The gate electrode is disposed on the semiconductor substrate, and the gate electrode overlaps a part of the well region in a thickness direction of the semiconductor substrate. A conductivity type of the gate electrode is complementary to a conductivity type of the well region for improving electrical performance of the variable capacitor.

Abstract: The present invention provides a method of decreasing program disturb in memory cells, comprising: finding an initial programming condition that ensure programming memory cell normally; selecting one parameter from the initial programming condition as a variable for the program disturb test; performing the program disturb test to the memory cell for at least two values of the variable; obtaining a programming condition with minimum program disturb based on the result of the program disturb test; and applying the programming condition with minimum program disturb as the programming condition for memory cell. The method according to the present invention can minimize the program disturb for the memory cell and can be performed easily.

Abstract: The present invention provides a method for decreasing program disturb in memory cells, comprising: finding an initial programming condition that ensures programming memory cell normally; selecting two parameters from the initial programming condition as variables for a program disturb test; performing the program disturb test to the memory cell for at least two combined values of the variables; obtaining a programming condition with minimum program disturb based on the result of the program disturb test; and applying the programming condition with minimum program disturb as the programming condition for memory cell. The method according to the present invention can minimize the program disturb in memory cells and can be performed easily.

Abstract: The present invention provides a method for decreasing program disturb in memory cells, comprising: finding an initial programming condition that ensures programming memory cell normally; selecting two parameters from the initial programming condition as variables for a program disturb test; performing the program disturb test to the memory cell for at least two combined values of the variables; obtaining a programming condition with minimum program disturb based on the result of the program disturb test; and applying the programming condition with minimum program disturb as the programming condition for memory cell. The method according to the present invention can minimize the program disturb in memory cells and can be performed easily.

Abstract: The present invention provides a method of decreasing program disturb in memory cells, comprising: finding an initial programming condition that ensure programming memory cell normally; selecting one parameter from the initial programming condition as a variable for the program disturb test; performing the program disturb test to the memory cell for at least two values of the variable; obtaining a programming condition with minimum program disturb based on the result of the program disturb test; and applying the programming condition with minimum program disturb as the programming condition for memory cell. The method according to the present invention can minimize the program disturb for the memory cell and can be performed easily.

Abstract: A novel structured for a diode-like PID protection (DLPP) device structure and process are described. An N-well, three associate N+ regions and a P+ region are formed on a P substrate. The DLPP is structured as a butting diode with a polysilicon gate above the butting region. The gate is connected to a metal antenna element and to the zener like trigger element of the device. The N-well functions as a resistor and capacitor buffer between the poly gate and antenna and the substrate. The antenna picks up a portion of the plasma charge to provide a gate voltage. There is an inversion layer or accumulation layer for positive or negative plasma charge formed under the poly gate. The junction of the effective zener diode is found in the interface between the N-type inversion layer and P+, or N+ and P-type accumulation layer. Changing the shape and the size of the antenna changes the gate voltage, and subsequently the trigger voltage of the DLPP.