Abstract: OLED-based devices that include at least two colors of emissive regions are provided, in which one region is optically coupled to a microcavity and the other is not. Devices including pixels in which only a portion of sub-pixels within the pixel are coupled to a microcavity are provided.

Abstract: Systems and techniques are provided that allow for fabrication of full-color OLED displays that include only two colors of emissive regions and four or more sub-pixels within pixels of the device. Mask arrangements for fabricating such devices are also provided.

Abstract: OLED-based devices that include at least two colors of emissive regions are provided, in which one region is optically coupled to a microcavity and the other is not. Devices including pixels in which only a portion of sub-pixels within the pixel are coupled to a microcavity are provided.

Abstract: OLED-based devices that include at least two colors of emissive regions are provided, in which one region is optically coupled to a microcavity and the other is not. Devices including pixels in which only a portion of sub-pixels within the pixel are coupled to a microcavity are provided.

Abstract: Systems and techniques are provided that allow for fabrication of full-color OLED displays that include only two colors of emissive regions and four or more sub-pixels within pixels of the device. Mask arrangements for fabricating such devices are also provided.

Abstract: A connection for mounting an IC die directly to a substrate includes circuit runs deposited on the substrate with bond pad portions having metallization patterns forming ridges and cutout areas. Metal bumps made of gold or other highly conductive malleable material are placed atop the metallization patterns and are forced into the cutout areas between ridges as the dies are compressed onto the substrate. This locks the dies to the circuit run bond pads so as to resist thermal stress and high humidity.

Abstract: A metal lead frame for an integrated circuit package is disclosed having stress relieving means formed therein to inhibit breakage of a thermally mismatched silicon die subsequently attached thereto and then heated during normal operation of the device. The stress relieving means may comprise parallel grooves formed in one or both surfaces of the central portion of the lead frame where a silicon integrated circuit die will subsequently be bonded to the lead frame. Preferably, the grooves are formed in both axes comprising the plane of the lead frame and may be formed on both surfaces of the lead frame. The stress relieving means may also comprise a series of openings cut through the central portion of the lead frame.

Abstract: The invention discloses an improved integrated circuit package having enhanced thermal conductivity comprising a molding or encapsulation resin having a semiconductor filler material. In a preferred embodiment, the semiconductor filler material comprises a high purity doped semiconductor to reduce alpha errors caused by alpha emisison normally caused by the use of fillers containing trace amounts of radioactive impurities and to provide enhanced thermal conductivity.

Abstract: A metal lead frame for an integrated circuit package is disclosed having stress relieving means formed therein to inhibit breakage of a thermally mismatched silicon die subsequently attached thereto and then heated during normal operation of the device. The stress relieving means may comprise parallel grooves formed in one or both surfaces of the central portion of the lead frame where a silicon integrated circuit die will subsequently be bonded to the lead frame. Preferably, the grooves are formed in both axes comprising the plane of the lead frame and may be formed on both surfaces of the lead frame. The stress relieving means may also comprise a series of openings cut through the central portion of the lead frame.

Abstract: A high performance test fixture is disclosed for testing integrated circuit chips which permits high throughput and good heat dissipation wherein flexible contact apparatus carried by said test fixture are urged into contact with the corresponding contacts on an integrated circuit chip using a pressurizable chamber wherein the flexible contact member carrying the test fixture contacts constitutes one wall of the chamber whereby pressurizing the chamber urges the flexible contact member and the contacts carried thereon against the chip. In a preferred embodiment, the chamber is pressurized by a cooling gas which compensates for the heat generated during the testing; and the test fixture is provided with apparatus to vibrate the contacts thereon in a lateral direction over the chip contacts to thereby remove oxide on the chip contacts to ensure a better electrical contact between the chip contacts and the test fixture contacts.

Abstract: An improved integrated circuit package is disclsoed which comprises a flexible lead frame assembly 2 having an integrated circuit die 60 mounted thereto. Lead frame assembly 2 comprises a first conductive metal layer 10 comprising metal leads 18 and 28 capable of being electrically connected to die 60, a flexible dielectric layer 30 attached to at least a portion of the first conductive metal layer 10, and a second metal conductive layer 40 having a portion attached to the opposite side of dielectric layer 30 and also comprising one or more leads 48, 54, and 56 capable of being electrically attached to the die, at least one of the metal layers 10 or 40 further comprises at least one metal bus pattern 12 or 32 or 42 with metal leads 18, 28, and 48 capable of being electrically attached to die 60.

Abstract: The invention discloses an improved PC board package for at least one integrated circuit die utilizing a plurality of PC boards bonded together to form a composite. The composite has at least one cavity, for mounting of an integrated circuit die, formed in at least one PC board of the composite. The cavity walls are plated to seal off portions of the PC board exposed by formation of the cavity to thereby prevent subsequent outgassing. Heat tubes are formed in a PC board adjacent the PC board with the cavity to conduct heat from an integrated circuit chip mounted in the cavity to an opposite surface of the package.

Abstract: The invention discloses an improved PC board package for one or more integrated circuit dies comprising a plurality of PC boards bonded together to form a composite. The composite has at least one cavity, for mounting of an integrated circuit die, formed in at least one PC board of the composite. The cavity walls are plated to seal off portions of the PC board exposed by formation of the cavity to thereby prevent subsequent outgassing. Heat pipes are formed in a PC board adjacent the PC board with the cavity to conduct heat from an integrated circuit chip mounted in the cavity to an opposite surface of the package.

Abstract: An improved package for a semiconductor device comprises an integrated circuit die and a mounting package having an array of parallel leads which directly connect perpendicular to the die. The process for making the package comprises forming an array of parallel, spaced apart, conductor pins; bonding the array of parallel conductor pins directly to an integrated circuit die while maintaining the die in a plane perpendicular to the parallel pins; and surrounding the die with a package material capable of protecting the die.