Abstract: The disclosure provides a chip package and an electronic device. The chip package includes: a package substrate, a semiconductor substrate provided on the package substrate and a first chip and a second chip provided on the semiconductor substrate. The semiconductor substrate includes a first group of pins and a second group of pins arranged on the semiconductor substrate and a connecting layer located between the first group of pins and the second group of pins. The connecting layer has a plurality of connecting channels, and the first group of pins and the second group of pins are connected through the plurality of connecting channels. The first chip has a third group of pins, the second chip has a fourth group of pins, and the third group of pins are connected to the first group of pins, and the fourth group of pins are connected to the second group of pins.

Abstract: Embodiments of the present disclosure relate to a method and apparatus for balancing loads, and a computer-readable storage medium. The method includes: for each data processing unit in a set of data processing units in a data processing system, acquiring current input data of the data processing unit for a current clock cycle and next input data of the data processing unit for a next clock cycle; and determining a first metric value indicating changes in input data of said data processing unit in the next clock cycle based on a comparison between the current input data and the next input data. The method further includes controlling an operating state of the set of data processing units in the next clock cycle based on the first metric value determined for the set of data processing units.

Abstract: The disclosure provides a chip package and an electronic device. The chip package includes: a package substrate, a semiconductor substrate provided on the package substrate and a first chip and a second chip provided on the semiconductor substrate. The semiconductor substrate includes a first group of pins and a second group of pins arranged on the semiconductor substrate and a connecting layer located between the first group of pins and the second group of pins. The connecting layer has a plurality of connecting channels, and the first group of pins and the second group of pins are connected through the plurality of connecting channels. The first chip has a third group of pins, the second chip has a fourth group of pins, and the third group of pins are connected to the first group of pins, and the fourth group of pins are connected to the second group of pins.

Abstract: Disclosed are an apparatus for data processing, an artificial intelligence chip, and an electronic device. The apparatus for data processing includes: at least one input memory, at least one data conveying component, at least one multiplexed arbitration component, and at least one output memory. The input memory is connected to the data conveying component, the data conveying component is connected to the multiplexed arbitration component, and the multiplexed arbitration component is connected to the output memory.

Abstract: Embodiments of the present disclosure relate to a method and apparatus for balancing loads, and a computer-readable storage medium. The method includes: for each data processing unit in a set of data processing units in a data processing system, acquiring current input data of the data processing unit for a current clock cycle and next input data of the data processing unit for a next clock cycle; and determining a first metric value indicating changes in input data of said data processing unit in the next clock cycle based on a comparison between the current input data and the next input data. The method further includes controlling an operating state of the set of data processing units in the next clock cycle based on the first metric value determined for the set of data processing units.

Abstract: Disclosed are an apparatus for data processing, an artificial intelligence chip, and an electronic device. The apparatus for data processing includes: at least one input memory, at least one data conveying component, at least one multiplexed arbitration component, and at least one output memory. The input memory is connected to the data conveying component, the data conveying component is connected to the multiplexed arbitration component, and the multiplexed arbitration component is connected to the output memory.