Abstract: Resonance reduction arrangements to reduce the impact of power supply resonance on circuits, comprising a resonance sensor and a charge dumper, wherein upon the detection of the predetermined resonance by the resonance sensor at a circuit location, the charge dumper dumps charges at least one of from and to the circuit location, wherein the charge dumper comprises at least one gating transistor to dump the charges, the at least one gating transistor is directly connected to a first power supply line having a first potential and a second power supply line having a second potential of a different potential than the first potential.

Abstract: A system is provided that includes a power distribution network to provide a switching current and a resonance reduction circuit to sense the switching current within a frequency range and to generate a resonance reduction signal having a current component at substantially a same frequency and substantially 180 degrees out of phase from the sensed switching current. The power distribution network may combine the switching current with the resonance reduction signal to provide a total switching current that may be provided to a processor as the powering signal.

Abstract: A method and apparatus for generating clock frequencies using cascaded phase-locked loop (PLL) circuits includes a first PLL circuit coupled to a second PLL circuit to produce a microprocessor I/O data clock signal and a microprocessor core clock signal, respectively. In one embodiment, the first PLL produces the data clock signal based upon a first reference signal and a first feedback signal, where the first feedback signal is derived from the data clock signal. Furthermore, the second PLL circuit produces the core clock signal based at least in part upon a second reference signal and a second feedback signal, where the second reference signal is derived from the data clock signal and the second feedback signal is derived from the core clock signal.

Abstract: A method and apparatus for generating clock frequencies using cascaded phase-locked loop (PLL) circuits includes a first PLL circuit coupled to a second PLL circuit to produce a microprocessor I/O data clock signal and a microprocessor core clock signal, respectively. In one embodiment, the first PLL produces the data clock signal based upon a first reference signal and a first feedback signal, where the first feedback signal is derived from the data clock signal. Furthermore, the second PLL circuit produces the core clock signal based at least in part upon a second reference signal and a second feedback signal, where the second reference signal is derived from the data clock signal and the second feedback signal is derived from the core clock signal.

Abstract: A system is provided that includes a power distribution network to provide a switching current and a resonance reduction circuit to sense the switching current within a frequency range and to generate a resonance reduction signal having a current component at substantially a same frequency and substantially 180 degrees out of phase from the sensed switching current. The power distribution network may combine the switching current with the resonance reduction signal to provide a total switching current that may be provided to a processor as the powering signal.

Abstract: Resonance reduction arrangements to reduce the impact of power supply resonance on circuits.

Abstract: A method for a fully digitally controlled delay element with wide delay tuning range and small tuning error. The method of one embodiment comprises receiving a set of digital control bits at a delay element. The set of digital control bits is to alter the amount of delay provided from the delay element to an input signal. A driving current through a first driver of the delay element is adjusted with the digital control bits. A capacitance on an output node of the delay element is adjusted with the digital control bits. The output is a delayed version of the input signal based on the driving current and the capacitance.

Abstract: The present invention is related to method and apparatus for reducing variations on damping factor and natural frequency in phase locked loops where a desired frequency range from a PLL is determined. A loop filter resistance of the PLL is adjustable to minimize variations on the damping factor of the PLL as the frequency of the PLL changes. Further, the frequency of an input clock to the PLL may be determined along with a value of a PLL frequency multiplier. A first ratio of the current in a first charge pump to a VCO tail current and a second ratio of the current in a second charge pump to the VCO tail current may be adjusted, where the first ratio and the second ratio are adjustable to minimize variations on the natural frequency of the PLL as the input clock frequency and/or the PLL multiplier value of the PLL changes.

Abstract: A clocked sense amplifier flip flop includes at least one keeper unit to prevent the occurrence of a floating data node.

Abstract: A static random access memory device used in a system having a data clock includes a recirculating counter producing a pair of clocking signals and n data latches each connected to a source of data chunks. Logic receiving a strobe signal, inverse strobe signal, and the clocking signals, successively latches serial data chunks into n data latches, respectively, such that a data chunk is latched one per each cycle of the data clock and so that every n data chunks form a group of parallel data. A delay circuit delaying certain ones of the data chunks latched into the input data latches long enough to permit all data chunks in a group to be transferred in parallel to further memory circuit, wherein the parallel transfer takes place once every n cycles of the data clock.