Patents by Inventor Cao Cheng

Cao Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Negative capacitance transistor with external ferroelectric structure
    Patent number: 11961897
    Abstract: A first fin structure is disposed over a substrate. The first fin structure contains a semiconductor material. A gate dielectric layer is disposed over upper and side surfaces of the first fin structure. A gate electrode layer is formed over the gate dielectric layer. A second fin structure is disposed over the substrate. The second fin structure is physically separated from the first fin structure and contains a ferroelectric material. The second fin structure is electrically coupled to the gate electrode layer.
    Type: Grant
    Filed: January 10, 2022
    Date of Patent: April 16, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chi-Hsing Hsu, Sai-Hooi Yeong, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang, Min Cao
  • Liquid Reservoirs, Cartridge Assemblies and Related Systems and Methods
    Publication number: 20240116047
    Abstract: Liquid reservoirs, cartridge assemblies and related systems and methods are disclosed. An example implementation includes an apparatus that includes a body, a cover, and a lid assembly. The body includes a top surface and a storage chamber having an opening at the top surface. The cover covers or is positioned within the opening of the storage chamber. The lid assembly is coupled to the top surface and covers the opening of the storage chamber. The top surface and the first portion define a plenum. The cover is at least one of piercable, breakable, or movable to allow the storage chamber to be fluidly coupled to the plenum without venting the plenum to atmosphere.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 11, 2024
    Inventors: Panteleimon Athanasiou, Beng Keong Ang, Justin Davidson, Norman Khoo, Heng Kuang Cheng, Hao Yu, Zhenning Cao
  • Metal oxide interlayer structure for nFET and pFET
    Patent number: 11916128
    Abstract: The present disclosure provides a method of forming a semiconductor device including an nFET structure and a pFET structure where each of the nFET and pFET structures include a semiconductor substrate and a gate trench. The method includes depositing an interfacial layer in each gate trench, depositing a first ferroelectric layer over the interfacial layer, removing the first ferroelectric layer from the nFET structure, depositing a metal oxide layer in each gate trench, depositing a second ferroelectric layer over the metal oxide layer, removing the second ferroelectric layer from the pFET structure, and depositing a gate electrode in each gate trench.
    Type: Grant
    Filed: February 27, 2023
    Date of Patent: February 27, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Min Cao, Pei-Yu Wang, Sai-Hooi Yeong, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang
  • Apparatus and method for providing passive amplification
    Patent number: 9183826
    Abstract: An apparatus comprises a substantially horn shaped structure configured to amplify sound from a speaker of a device wherein the apparatus comprises packaging of the device.
    Type: Grant
    Filed: December 2, 2009
    Date of Patent: November 10, 2015
    Assignee: Nokia Technologies Oy
    Inventors: Jyri Salomaa, Nan Jiang, Cao Cheng, Leslie Fan, Ronan Jezequel
  • Apparatus
    Publication number: 20120237058
    Abstract: An apparatus comprises a substantially horn shaped structure configured to amplify sound from a speaker of a device wherein the apparatus comprises packaging of the device.
    Type: Application
    Filed: December 2, 2009
    Publication date: September 20, 2012
    Applicant: NOKIA CORPORATION
    Inventors: Jyri Salomaa, Nan Jiang, Cao Cheng, Leslie Fan, Ronan Jezequel