Abstract: In a multiple access network a main station is to be capable of distinguishing signals transmitted by sub-stations to the main station. A method of realising this is the use of SCMA (SubCarder Multiple Access). According to this method the signal to be transmitted is modulated on a subcarrier having its own frequency and then modulated on a main carrier in each sub-station. In prior-art multiple access network the distribution signals which are to be transmitted to the sub-stations by the main station are modulated each on its own distribution subcarrier and then applied to a shared distribution modulator. For diminishing the requirements posed on the high-frequency properties of the electronic components necessary for the network, the subcarriers for distribution signals and return signals are selected to lie in the same frequency band.

Abstract: In a multiple access network the signals transmitted by a plurality of sub-stations to a main station over a common channel must be distinguished for each sub-station. A method of achieving this is to employ SCMA (Subcarrier Multiple Access), according to which in each sub-station the transmit signal is modulated on a subcarrier having a different frequency for each substation, and the modulated subcarrier amplitude modulates a main carrier which has substantially the same frequency for all sub-stations. To minimize mutual interference between sub-stations, according to the invention the amplitude of the main carrier transmitted by a sub-station is reduced during intervals in which the modulated auxiliary signal from that sub-station is not present or is at a zero reference level. In this way the number of modulated carrier signals which are present at any given time is reduced. Mutual interference is thereby significantly reduced, because it depends on the squared number of carriers present in the system.

Abstract: A data processing system based on (n, k) symbol code having symbol error correctability and plural error mendability is provided. The data processing system includes a decoder stage, a processor stage fed by the decoder stage, an encoding stage for receiving data words from the processor stage, a memory stage for receiving code words from the processor stage and a feedback stage for retro-coupling code words to the decoder stage. The data processing system includes at least two data processing units, each unit including more than one but less than n different encoder modules.

Abstract: In a data processing device which consists of a plurality of parallel-operating modules, each of the four modules is provided with its own clock circuit. Synchronization is realized at the level of the cycle of the high frequency oscillation. This is realized in that each of the clock circuits includes a two-out-of-three majority decision device which is fed by the output clock signals of the other three clock circuits. The majority decision may have a simple logic structure and is connected to the actual clock function generator in order to reduce, using a readjustment circuit, the deviation between the clock function signal and the majority signal by a factor substantially smaller than one for each transition of the majority signal.