Patents by Inventor Carl A. Malmquist

Carl A. Malmquist has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Coupled synchronous-asychronous bus structure for transferring data between a plurality of peripheral input/output controllers and a main data store
    Patent number: 5509124
    Abstract: In a data processing system, an input output bus unit (IOBU) is connected to one end of an input output interface controller (IOIC) via an asynchronous bus. The other end of the IOIC is connected to a storage controller (SC) and an input output interface unit (IOIU) via a synchronous bus. The SC and IOIU are connected to a memory unit and an instruction processing unit. The asynchronous bus, which is comprised of three sub-buses and a control bus, conducts signals between the IOIC and an IOBU in an asynchronous "handshaking" manner. The synchronous bus, which is comprised of two sub-buses and a control bus, conducts signals between the IOIC and the SC/IOIU in an synchronous manner. The IOIC, interconnected between the synchronous bus and asynchronous bus, functions as a buffer between the faster synchronous bus and the slower asynchronous bus.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: April 16, 1996
    Assignee: International Business Machines Corporation
    Inventors: Donall G. Bourke, Douglas R. Chisholm, Gregory D. Float, Richard A. Kelley, Roy Y. Liu, Carl A. Malmquist, John M. Nelson, Charles B. Perkins, Jr., Richard L. Place, Hartmut R. Schwermer, John D. Wilson
  • Method for performing inter-unit data transfer operations among a plurality of input/output bus interface units coupled to a common asynchronous bus
    Patent number: 5455916
    Abstract: In a data processing system, an input output bus unit (IOBU) is connected to one end of an input output interface controller (IOIC) via an asynchronous bus. The other end of the IOIC is connected to a storage controller (SC) and an input output interface unit (IOIU) via a synchronous bus. The SC and IOIU are connected to a memory unit and an instruction processing unit. The asynchronous bus, which is comprised of three sub-buses and a control bus, conducts signals between the IOIC and an IOBU in an asynchronous "handshaking" manner. The synchronous bus, which is comprised of two sub-buses and a control bus, conducts signals between the IOIC and the SC/IOIU in an synchronous manner. The IOIC, interconnected between the synchronous bus and asynchronous bus, functions as a buffer between the faster synchronous bus and the slower asynchronous bus.
    Type: Grant
    Filed: January 10, 1995
    Date of Patent: October 3, 1995
    Assignee: International Business Machines Corporation
    Inventors: Donall G. Bourke, Douglas R. Chisholm, Gregory D. Float, Richard A. Kelley, Roy Y. Liu, Carl A. Malmquist, John M. Nelson, Charles B. Perkins, Jr., Richard L. Place, Hartmut R. Schwermer, John D. Wilson
  • Method for transferring information between main store and input output bus units via a sequence of asynchronous bus and two synchronous buses
    Patent number: 5276814
    Abstract: In a data processing system, an input output bus unit (IOBU) is connected one end of an input output interface controller (IOIC) via an asynchronous bus. The other end of the IOIC is connected to a storage controller (SC) and an input output interface unit (IOIU) via a synchronous bus. The SC and IOIU are connected to a memory unit and an instruction processing unit. The asynchronous bus, which is comprised of three sub-buses and a control bus, conducts signals between the IOIC and an IOBU in an asynchronous handshaking manner. The synchronous bus, which is comprised of two sub-buses and a control bus, conducts signals between the IOIC and the SC/IOIU in an synchronous manner. The IOIC, interconnected between the synchronous bus and asynchronous bus, functions as a buffer between the faster synchronous bus and the slower asynchronous bus. Various operations are performed between an IOBU and the memory unit via the asynchronous bus, IOIC, synchronous bus, message acceptance operation.
    Type: Grant
    Filed: May 10, 1989
    Date of Patent: January 4, 1994
    Assignee: International Business Machines Corporation
    Inventors: Donall G. Bourke, Douglas R. Chisholm, Gregory D. Float, Richard A. Kelley, Roy Y. Liu, Carl A. Malmquist, John M. Nelson, Charles B. Perkins, Jr., Richard L. Place, Hartmut R. Schwermer, John D. Wilson
  • Input output interface controller connecting a synchronous bus to an asynchronous bus and methods for performing operations on the bus
    Patent number: 5199106
    Abstract: In a data processing system, an input output bus unit (IOBU) is connected to one end of an input output interface controller (IOIC) via an asynchronous bus. The other end of the IOIC is connected to a storage controller (SC) and an input output interface unit (IOIU) via a synchronous bus. The SC and IOIU are connected to a memory unit and an instruction processing unit. The asynchronous bus, which is comprised of three sub-buses and a control bus, conducts signals between the IOIC and an IOBU in an asynchronous "handshaking" manner. The synchronous bus, which is comprised of two sub-buses and a control bus, conducts signals between the IOIC and the SC/IOIU in an synchronous manner. The IOIC, interconnected between the synchronous bus and asynchronous bus, functions as a buffer between the faster synchronous bus and the slower asynchronous bus.
    Type: Grant
    Filed: August 15, 1990
    Date of Patent: March 30, 1993
    Assignee: International Business Machines Corporation
    Inventors: Donall G. Bourke, Douglas R. Chisholm, Gregory D. Float, Richard A. Kelley, Roy Y. Liu, Carl A. Malmquist, John M. Nelson, Charles B. Perkins, Jr., Richard L. Place, Hartmut R. Schwermer, John D. Wilson
  • Arbitration apparatus for determining priority of access to a shared bus on a rotating priority basis
    Patent number: 4760515
    Abstract: An arbitration apparatus for use within a computer system comprises a plurality of individual arbiters arranged in a particular configuration wherein some individual arbiters are higher in the particular configuration than a specific arbiter and some individual arbiters are lower in the particular configuration than the specific arbiter. Each arbiter has a request terminal for receiving access request signals, requesting access to a shared system bus, and an enable terminal for receiving an enabling signal. The enabling signal is generated and energizes the enable terminal of the specific arbiter if access requests are not received by higher arbiters in the particular configuration relative to the specific arbiter. If an access request signal energizes an arbiter and an enabling signal energizes the arbiter, an access grant signal is developed from the arbiter.
    Type: Grant
    Filed: October 28, 1985
    Date of Patent: July 26, 1988
    Assignee: International Business Machines Corporation
    Inventors: Carl A. Malmquist, John D. Wilson