Patents by Inventor Carl A. Monzel
Carl A. Monzel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9753667Abstract: A high-bandwidth multiple-read memory device includes multiple memory blocks, multiple address input buses, and a number of output data buses. The memory blocks include an auxiliary memory block and each memory block include several memory sub-blocks including an auxiliary memory sub-block. The output data buses output data corresponding to addresses corresponding to the address input buses during a multiple-read operation. The addresses correspond to a single memory sub-block of the memory sub-blocks of a memory block. Also described is differential XOR circuit that includes a selection logic circuit, a precharger circuit, and a multiplexer. The selection logic circuit provides a complementary output signal corresponding to a single-ended input signal. The multiplexer provides, during an evaluate phase, a differential output signal.Type: GrantFiled: March 10, 2015Date of Patent: September 5, 2017Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.Inventors: Travis Hebig, Myron Buer, Carl Monzel, Richard John Stephani
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Publication number: 20160246506Abstract: A high-bandwidth multiple-read memory device includes multiple memory blocks, multiple address input buses, and a number of output data buses. The memory blocks include an auxiliary memory block and each memory block include several memory sub-blocks including an auxiliary memory sub-block. The output data buses output data corresponding to addresses corresponding to the address input buses during a multiple-read operation. The addresses correspond to a single memory sub-block of the memory sub-blocks of a memory block. Also described is differential XOR circuit that includes a selection logic circuit, a precharger circuit, and a multiplexer. The selection logic circuit provides a complementary output signal corresponding to a single-ended input signal. The multiplexer provides, during an evaluate phase, a differential output signal.Type: ApplicationFiled: March 10, 2015Publication date: August 25, 2016Inventors: Travis HEBIG, Myron BUER, Carl MONZEL, Richard John STEPHANI
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Patent number: 9324451Abstract: A device for monitoring process variations across memory bitcells includes a bitcell inverter that provides an output voltage to be used for identifying skewed corners of the memory bitcells. A first comparator compares the output voltage with a first reference voltage, and a second comparator compares the output voltage with a second reference voltage. The first and the second comparators generate a corner code based on comparison results.Type: GrantFiled: November 6, 2014Date of Patent: April 26, 2016Assignee: Broadcom CorporationInventors: Saket Gupta, Yifei Zhang, Carl Monzel, Mark Jon Winter
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Publication number: 20160093399Abstract: A device for monitoring process variations across memory bitcells includes a bitcell inverter that provides an output voltage to be used for identifying skewed corners of the memory bitcells. A first comparator compares the output voltage with a first reference voltage, and a second comparator compares the output voltage with a second reference voltage. The first and the second comparators generate a corner code based on comparison results.Type: ApplicationFiled: November 6, 2014Publication date: March 31, 2016Inventors: Saket GUPTA, Yifei ZHANG, Carl MONZEL, Mark Jon WINTER
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Patent number: 8705268Abstract: Yield loss from peripheral circuit failure while screening memory arrays for aging effects is prevented by operating the peripheral circuitry at nominal operating voltages during the screening for aging effects. An integrated circuit including one or more memory bit cells, includes circuitry to change the voltage applied to the supply rails of bit cells and the voltage applied to the word-line drivers relative to each other in order to facilitate improved screening for read and write margins. In normal operation the supply rails for word-line drivers and bit cells are nominally the same. In a write margin test mode the voltage on the supply rail of word-line drivers is lower than the voltage on the supply rail of the bit cells. In a read margin test mode the voltage on the supply rail of word-line drivers is higher than the voltage on the supply rail of the bit cells.Type: GrantFiled: December 27, 2011Date of Patent: April 22, 2014Assignee: Broadcom CorporationInventors: Myron Buer, Carl Monzel, Yifei Zhang
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Publication number: 20130163357Abstract: Yield loss from peripheral circuit failure while screening memory arrays for aging effects is prevented by operating the peripheral circuitry at nominal operating voltages during the screening for aging effects. An integrated circuit including one or more memory bit cells, includes circuitry to change the voltage applied to the supply rails of bit cells and the voltage applied to the word-line drivers relative to each other in order to facilitate improved screening for read and write margins. In normal operation the supply rails for word-line drivers and bit cells are nominally the same. In a write margin test mode the voltage on the supply rail of word-line drivers is lower than the voltage on the supply rail of the bit cells. In a read margin test mode the voltage on the supply rail of word-line drivers is higher than the voltage on the supply rail of the bit cells.Type: ApplicationFiled: December 27, 2011Publication date: June 27, 2013Applicant: Broadcom CorporationInventors: Myron Buer, Carl Monzel, Yifei Zhang
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Patent number: 8429586Abstract: A basic cell circuit architecture having plurality of cells with fixed transistors configurable for the formation of logic devices and single and dual port memory devices within a structured ASIC is provided. Different configurations of ensuing integrated circuits are achieved by forming variable interconnect layers above the fixed structures. The circuit architecture can achieve interconnection of transistors within a single cell or across multiple cells. The interconnection can be configured to form basic logic gates as well as more complex digital and analog subsystems. In addition, each cell contains a layout of transistors that can be variably coupled to achieve a memory device, such as a SRAM device. By having the capability of forming a logic circuit element, a memory device, or both, the circuit architecture is both memory-centric and logic-centric, and more fully adaptable to modern-day SoCs.Type: GrantFiled: March 20, 2012Date of Patent: April 23, 2013Assignee: LSI CorporationInventors: Ramnath Venkatraman, Michael N. Dillon, David A. Gardner, Carl A. Monzel, III, Subramanian Ramesh, Robert C. Armstrong, Gary S. Delp, Scott A. Peterson
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Patent number: 7190185Abstract: A test methodology which provides that test structures, such as transistors, are arranged in a plurality of rows. A logic circuit controls which row is to be measured. An incrementer receives a triggering signal and functions as an address adder. Each time the triggering signal rises from 0 to 1, the output of the incrementer increases by 1. The output of the incrementer serves as the address input into a decoder. The decoder is connected to the rows of test structures. Preferably, each test structure contains a control circuit which is controlled by this signal (i.e., the output of the decoder). If the test structures are transistors, bias to each of the transistors can be applied separately with a common gate, source and well, and measurement can be done with a separate drain node.Type: GrantFiled: October 29, 2003Date of Patent: March 13, 2007Assignee: LSI Logic CorporationInventors: Franklin Duan, Minxuan Liu, John Walker, Nabil Monsour, Carl Monzel
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Publication number: 20050093560Abstract: A test methodology which provides that test structures, such as transistors, are arranged in a plurality of rows. A logic circuit controls which row is to be measured. An incrementer receives a triggering signal and functions as an address adder. Each time the triggering signal rises from 0 to 1, the output of the incrementer increases by 1. The output of the incrementer serves as the address input into a decoder. The decoder is connected to the rows of test structures. Preferably, each test structure contains a control circuit which is controlled by this signal (i.e., the output of the decoder). If the test structures are transistors, bias to each of the transistors can be applied separately with a common gate, source and well, and measurement can be done with a separate drain node.Type: ApplicationFiled: October 29, 2003Publication date: May 5, 2005Inventors: Franklin Duan, Minxuan Liu, John Walker, Nabil Mansour, Carl Monzel
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Patent number: 6879524Abstract: A memory input-output (IO) buffer is provided, which includes a bit line, a data input-output line and a combined sense amplifier and write driver. The combined sense amplifier and write driver is coupled to the data input-output line and the first bit line and shares the same physical area on an integrated circuit.Type: GrantFiled: September 19, 2002Date of Patent: April 12, 2005Assignee: LSI Logic CorporationInventor: Carl A. Monzel
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Patent number: 6734744Abstract: A process monitor circuit useful for integrated circuit designs to provide manufacturing process tests for SRAM circuit structures incorporated in an integrated circuit design. In one aspect of the invention, the process monitor cell includes a plurality of SRAM circuit cells chained together in a manner to permit testing of a desired range of SRAM transistor power and a desired range of associated propagation delays. The process monitor cell thereby provides an accurate estimate of the quality of the fabrication process used to generate other functional SRAM cells within the integrated circuit design.Type: GrantFiled: September 30, 2002Date of Patent: May 11, 2004Assignee: LSI Logic CorporationInventors: Carl A. Monzel, Brandon R. Bartz
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Publication number: 20040061561Abstract: A process monitor circuit useful for integrated circuit designs to provide manufacturing process tests for SRAM circuit structures incorporated in an integrated circuit design. In one aspect of the invention, the process monitor cell includes a plurality of SRAM circuit cells chained together in a manner to permit testing of a desired range of SRAM transistor power and a desired range of associated propagation delays. The process monitor cell thereby provides an accurate estimate of the quality of the fabrication process used to generate other functional SRAM cells within the integrated circuit design.Type: ApplicationFiled: September 30, 2002Publication date: April 1, 2004Inventors: Carl A. Monzel, Brandon R. Bartz
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Publication number: 20040057290Abstract: A memory input-output (IO) buffer is provided, which includes a bit line, a data input-output line and a combined sense amplifier and write driver. The combined sense amplifier and write driver is coupled to the data input-output line and the first bit line and shares the same physical area on an integrated circuit.Type: ApplicationFiled: September 19, 2002Publication date: March 25, 2004Inventor: Carl A. Monzel
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Patent number: 6687183Abstract: A method for changing the internal timing of a memory to allow adjustment of the access time of the memory to be faster or slower by increasing or decreasing internal margins of the memory (bit line separation), respectively, utilizes the memory compiler for setting the number of core cells used for driving a self time column of the memory.Type: GrantFiled: November 27, 2001Date of Patent: February 3, 2004Assignee: LSI Logic CorporationInventors: Steven M. Peterson, Sifang Wu, Mai Mac Lennan, Carl A. Monzel
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Patent number: 6667912Abstract: A semiconductor memory device includes at least one memory cell for storing digital data. A local sense amplifier is operably coupled to the at least one memory cell for receiving a first signal representative of the digital data stored in the at least one memory cell, and outputting a second signal representative of the received first signal in response to a first strobe signal. A global sense amplifier is operably coupled to the local sense amplifier for receiving the second signal, and outputting a third signal representative of the received second signal in response to a second strobe signal. Dummy circuitry is provided for-enabling generation of the first and second strobe signals.Type: GrantFiled: February 18, 2002Date of Patent: December 23, 2003Assignee: LSI Logic CorporationInventor: Carl A. Monzel
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Publication number: 20030099128Abstract: A method for changing the internal timing of a memory to allow adjustment of the access time of the memory to be faster or slower by increasing or decreasing internal margins of the memory (bit line separation), respectively, utilizes the memory compiler for setting the number of core cells used for driving a self time column of the memory.Type: ApplicationFiled: November 27, 2001Publication date: May 29, 2003Inventors: Steven M. Peterson, Sifang Wu, Mai MacLennan, Carl A. Monzel
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Patent number: 6542434Abstract: A programmable self time circuit for controlling bit line separation in a memory includes multiple self time word lines, each of which is connected to at least one core cell of the memory for activating the cell. The self time word lines have enable signals that can either be programmed on/off, or can be externally controlled for variation of the amount of bit line separation developed during a memory access.Type: GrantFiled: May 31, 2001Date of Patent: April 1, 2003Assignee: LSI Logic CorporationInventor: Carl A. Monzel
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Patent number: 6498758Abstract: A method for reducing electrical coupling within a computer multi-port memory cell array is provided. The method comprises twisting complementary wires of a first, inner bit line pair in a first memory cell column, wherein the twisting reverses the complementary wires, and wherein the physical twisting occurs in odd numbered dummy rows, twice along a column. The complementary wires of a second, outer bit line pair in the same column, wherein the physical twisting occurs in even numbered dummy rows, once along the column. The complementary wires of a third, inner bit line pair in a second memory cell column are then twisted, wherein the physical twisting occurs in even numbered dummy rows, once along the column, and the complementary wires of a fourth, outer bit line pair in the second column are twisted in odd numbered dummy rows, twice along the column.Type: GrantFiled: January 16, 2002Date of Patent: December 24, 2002Assignee: LSI Logic CorporationInventors: Sudeep A. Pomar, Carl A. Monzel