Abstract: An electrode assembly is described that can be implanted in target tissue of a living body. The electrode assembly includes an introduction needle, a flexible leader coupled to the introduction needle, and an elongated electrode with fixation mechanisms on its proximal and distal ends. The introduction needle includes a visible marker that is a fixed distance from the pointed tip of the needle. This distance is approximately the same as the length of the electrode. During implantation, a surgeon penetrates the tissue with the introduction needle, thereby creating a tract in the tissue, and drives the needle in the tissue up to the marker, then perforates the tissue to cause the needle to emerge. This creates a tract that is approximately the same length as the electrode. The electrode can be pulled into the tract, where the fixation mechanisms resist migration from the tract.

Abstract: A needle driver is described that can be used to drive a plurality of surgical needles into or proximate to tissue of a living body. The needle driver assists the surgeon in perforating the tissue, creating the tracts at a desired depth, and creating multiple tracts simultaneously. The needle driver is configured to hold the needles securely when creating the tracts, and is also configured to disengage from the needles after the tracts have been created.

Abstract: A method and an apparatus for synchronizing clock domains. A slow clock signal is received. A circuit in a slow clock domain is operated based upon the slow clock signal. A fast clock signal is received. The slow clock signal is synchronized using the fast clock signal. The operation of the circuit is modified from the slow clock domain to the fast clock domain, modifying the operation comprising changing a clock operation frequency during a non-transition period of the slow clock.

Abstract: A method and an apparatus for a hardware/firmware trap. At least one set of a firmware code is executed for operation of the device. Modification to the operation of the device is performed. The modification to the operation comprises: receiving a patch code; creating a firmware trap; generating an interrupt in response to the firmware trap; and executing the patch code in response to the interrupt.

Abstract: A method and an apparatus for a hardware/firmware trap. At least one set of a firmware code is executed for operation of the device. Modification to the operation of the device is performed. The modification to the operation comprises: receiving a patch code; creating a firmware trap; generating an interrupt in response to the firmware trap; and executing the patch code in response to the interrupt.

Abstract: The present invention provides methods and systems for regulating delivery of therapeutic proteins and nucleic acids.

Abstract: A method and an apparatus for synchronizing clock domains. A slow clock signal is received. A circuit in a slow clock domain is operated based upon the slow clock signal. A fast clock signal is received. The slow clock signal is synchronized using the fast clock signal. The operation of the circuit is modified from the slow clock domain to the fast clock domain, modifying the operation comprising changing a clock operation frequency during a non-transition period of the slow clock.

Abstract: A system for minimizing power dissipation within an implantable medical device through use of adiabatic logic is disclosed. The system includes a first and a second sub-circuit of the implantable medical device. An electrical connection interconnects the first and the second sub-circuits, the electrical connection including a capacitive element. Circuitry, which charges the capacitive element of the electrical connection to generate a ramp logic signal, is connected to the capacitive element. The ramp logic signal includes a frequency of less than 500 kilohertz, thereby creating a low frequency, low power system which reduces energy dissipation to the surrounding environment.

Abstract: A system for minimizing power dissipation within an implantable medical device through use of adiabatic logic is disclosed. The system includes a first and a second sub-circuit of the implantable medical device. An electrical connection interconnects the first and the second sub-circuits, the electrical connection including a capacitive element. Circuitry, which charges the capacitive element of the electrical connection to generate a ramp logic signal, is connected to the capacitive element. The ramp logic signal includes a frequency of less than 500 kilohertz, thereby creating a low frequency, low power system which reduces energy dissipation to the surrounding environment.

Abstract: A method and an apparatus for a hardware/firmware trap. At least one set of a firmware code is executed for operation of the device. Modification to the operation of the device is performed. The modification to the operation comprises: receiving a patch code; creating a firmware trap; generating an interrupt in response to the firmware trap; and executing the patch code in response to the interrupt.

Abstract: Improved operating system architecture for an implantable medical device incorporating self-timed logic for reducing power consumption and increasing and improving processing capabilities is disclosed. The self-timed logic is employed to implement digital signal processors (DSPs) including analog to digital (ADC) signal converters, a state machine or the components of microprocessor cores, e.g., the CPU, arithmetic logic units (ALU), on-chip RAM and ROM and data and control buses, and other logic units, e.g., additional RAM and ROM, a direct memory address (DMA) controller, a block mover/reader, a cyclic redundancy code (CRC) calculator, and certain uplink and downlink telemetry signal processing stages. The self-timed CMOS logic is incorporated into the same IC or ICs with clocked CMOS logic in a manner that minimizes the size of the clock tree serving the clocked CMOS logic, allows for efficient allocation of chip real estate, and provides manufacturing economies.

Abstract: Improved operating system architecture for an implantable medical device incorporating adiabatic clock-powered logic alone or in conjunction with conventional clocked logic or self-timed logic for reducing power consumption and increasing and improving processing capabilities is disclosed. The adiabatic clock-powered logic is employed to implement digital signal processors (DSPs) including analog to digital (ADC) signal converters, a state machine or the components of microprocessor cores, e.g., the CPU, arithmetic logic units (ALU), on-chip RAM and ROM and data and control buses, and other logic units, e.g., additional RAM and ROM, a direct memory address (DMA) controller, a block mover/reader, a cyclic redundancy code (CRC) calculator, and certain uplink and downlink telemetry signal processing stages. The adiabatic clocked CMOS logic is incorporated into the same IC or ICs with clocked CMOS logic and provides manufacturing economies.

Abstract: Improved operating system architecture for an implantable medical device incorporating self-timed logic for reducing power consumption and increasing and improving processing capabilities is disclosed. The self-timed logic is employed to implement digital signal processors (DSPs) including analog to digital (ADC) signal converters, a state machine or the components of microprocessor cores, e.g., the CPU, arithmetic logic units (ALU), on-chip RAM and ROM and data and control buses, and other logic units, e.g., additional RAM and ROM, a direct memory address (DMA) controller, a block mover/reader, a cyclic redundancy code (CRC) calculator, and certain uplink and downlink telemetry signal processing stages. The self-timed CMOS logic is incorporated into the same IC or ICs with clocked CMOS logic in a manner that minimizes the size of the clock tree serving the clocked CMOS logic, allows for efficient allocation of chip real estate, and provides manufacturing economies.

Abstract: A method or apparatus for conserving power in an implantable medical device (IMD) of the type having at least one IC powered by a battery wherein, in each such IC, a voltage dependent oscillator for providing oscillator output signals at an oscillation frequency dependent upon applied supply voltage to the IC is incorporated into the IC. The voltage dependent oscillator oscillates at a frequency that is characteristic of the switching speed of all logic circuitry on the IC die that can be attained with the applied supply voltage. The applied supply voltage is regulated so that the oscillation frequency is maintained at no less than a target or desired oscillation frequency or within a desired oscillation frequency range. The power supply voltage that is applied to the IC is based directly on the performance of all logic circuitry of the IC.

Abstract: A cyclic redundancy code (CRC) and optionally a syndrome value calculation of one or more implantable medical device (IMD) data block is conducted by block mover/reader hardware of the IMD when the data block(s) are moved and/or read. In the block read operation, each data byte or word in the block mover data register is read in a first clock cycle. In the block move operation, each data byte is read in the first clock cycle in this way and then moved to a destination register in a second clock cycle. The data CRC and optionally the syndrome value accumulate in the CRC and syndrome registers as all data bytes of the data block(s) are read in the first clock cycle.

Abstract: An apparatus and method for protecting memory content of a programmable memory is disclosed. A programmable memory, such as a random access memory (RAM), is configured to include a write protected portion defined as part of the programmable memory. The write protected memory portion may be configured within the memory space of a single programmable memory, or implemented in a logically or physically separate programmable memory. A microprocessor is coupled to the programmable memory and generates an access code for providing write access to the write protected portion of the programmable memory. A logic circuit, coupled to the programmable memory and microprocessor verifies the access code received from the microprocessor. In response to a verified access code, the logic circuit enables write access to the write protected portion of the programmable memory. In response to an unverified access code, the logic circuit disables write access to the write protected portion of the programmable memory.

Abstract: An apparatus and method for controlling power in digital logic circuitry is disposed in a body implantable biomedical device disclosed. A power switch, such as a power gating transistor, is coupled to a digital logic circuit element to selectively control the application of power to the circuit element. During each system clock cycle, power is supplied to the circuit element only for a duration of time required to effect switching of logic states. Power is removed from the circuit element during each system clock cycle when no switching of logic states occurs. A clock signal applied to the gate of a power gating transistor selectively controls the supply of power to the digital circuit logic element during each system clock cycle so as to appreciably reduce static power consumption of the circuit element.