Abstract: A microprocessor includes a direct access memory (DMA) engine which is responsive to pairs of block indices associated with one or more blocks in a first logical plane and transfers the one or more blocks between the first logical plane, a second logical plane, and a physical memory space according to the pairs of block indices. The logical planes represent two dimensional fields of data such as those found in images and videos. The microprocessor further comprises cache memory which updates its content with one or more cache-blocks which are in the neighborhood of the one or more blocks improving the operation of the cache memory by increasing cache hits. The DMA engine may further operate on n-dimensional blocks in a n-dimensional logical space. The microprocessor further includes special-purpose instructions, operative on a single-instruction-multiple-data (SIMD) computation unit, especially tailored to perform matrix operations.

Abstract: Embodiments of the invention relate to data structure traversal instructions that perform efficient data structure traversal operations in packet processing applications. In one embodiment, a data structure traversal instruction for use in packet processing includes a control. In response to the control, the data structure traversal instruction accesses at least one node of a data structure. The data structure is typically a linked list or a binary tree. In an exemplary environment, the data structure traversal instruction may be implemented by a packet processor core of packet processor in a network device. In particular, three data structure traversal instructions are disclosed for accessing a node in a linked list and returning a data field, searching for a key value in a node of linked list, and accessing a node in a binary tree and searching for a matching key value, respectively.

Abstract: New instruction definitions for a packet add (PADD) operation and for a single instruction multiple add (SMAD) operation are disclosed. In addition, a new dedicated PADD logic device that performs the PADD operation in about one to two processor clock cycles is disclosed. Also, a new dedicated SMAD logic device that performs a single instruction multiple data add (SMAD) operation in about one to two clock cycles is disclosed.

Abstract: According to some embodiments, an instruction is pre-decoded at a direct memory access unit.

Abstract: Embodiments of the invention relate to bit manipulation instructions that perform efficient bit manipulation operations for packet processing applications. In one embodiment, a bit manipulation instruction for use in packet processing includes a control. In response to the control, the bit manipulation instruction selects a plurality of bits from a source register and writes the selected plurality of bits into a destination register in a manner designated by the control. In an exemplary environment, the bit manipulation instruction may be implemented by a packet processor core of packet processor in a network device. In particular, five bit manipulation instructions for bit extraction, bit packing, bit setting, bit unpacking, and bit matching operations will be disclosed. These instructions are particularly useful for packet processing applications.