Patents by Inventor Carl Anthony Monzel
Carl Anthony Monzel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170206948Abstract: Encoded bitlines run globally through a memory architecture. The encoded bitlines carry an encoded representation of the data bits read from memory cells. As a specific example, the encoded representation may be carried on encoded global bitlines in an SRAM memory architecture. The encoded representation reduces power consumption when used in conjunction with bitline pre-charging or pre-discharging. The encoding technique may be implemented in circuitry other than memories and applied to any type of signal bus, e.g., for address, data, or control signals, running between any types of circuitry.Type: ApplicationFiled: January 21, 2016Publication date: July 20, 2017Inventors: Travis Reynold Hebig, Ronald Daniel lsliefson, Carl Anthony Monzel, III, Myron James Buer
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Publication number: 20120175683Abstract: A basic cell circuit architecture having plurality of cells with fixed transistors configurable for the formation of logic devices and single and dual port memory devices within a structured ASIC is provided. Different configurations of ensuing integrated circuits are achieved by forming variable interconnect layers above the fixed structures. The circuit architecture can achieve interconnection of transistors within a single cell or across multiple cells. The interconnection can be configured to form basic logic gates as well as more complex digital and analog subsystems. In addition, each cell contains a layout of transistors that can be variably coupled to achieve a memory device, such as a SRAM device. By having the capability of forming a logic circuit element, a memory device, or both, the circuit architecture is both memory-centric and logic-centric, and more fully adaptable to modern-day SoCs.Type: ApplicationFiled: March 20, 2012Publication date: July 12, 2012Applicant: LSI CorporationInventors: Ramnath Venkatraman, Michael N. Dillon, David A. Gardner, Carl Anthony Monzel, III, Subramanian Ramesh, Robert C. Armstrong, Gary Scott Delp, Scott Allen Peterson
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Patent number: 8178909Abstract: An improved integrated circuit cell architecture is provided for configurability between a memory cell or logic elements. The cell architecture is configured on variable layers above a first layer of metal, with the first layer of metal and layers therebelow reserved as fixed layers. By coupling a maximum of two layout cells together, a single-port or dual-port memory cell is realized. Likewise, by interconnecting transistors within a single cell or transistors among two or more cells, a logic device is realized. Within each cell, the bit lines are arranged on a layer separate from the wordlines, and extend orthogonal to each other.Type: GrantFiled: September 23, 2011Date of Patent: May 15, 2012Assignee: LSI CorporationInventors: Ramnath Venkatraman, Carl Anthony Monzel, III, Subramanian Ramesh
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Patent number: 8166440Abstract: A basic cell circuit architecture having plurality of cells with fixed transistors configurable for the formation of logic devices and/or single/dual port memory devices within a structured ASIC is provided. Different configurations of ensuing integrated circuits are achieved by forming variable interconnect layers above the fixed structures. The circuit architecture can achieve interconnection of transistors within a single cell and/or across multiple cells. The interconnection can be configured to form basic logic gates as well as more complex digital and analog subsystems. In addition, each cell contains a layout of transistors that can be variably coupled to achieve a memory device, such as a SRAM device. By having the capability of forming either a logic circuit element, a memory device, or both, the circuit architecture is both memory-centric and logic-centric, and more fully adaptable to modern-day SoCs.Type: GrantFiled: June 16, 2008Date of Patent: April 24, 2012Assignee: LSI CorporationInventors: Ramnath Venkatraman, Michael N. Dillon, David A. Gardner, Carl Anthony Monzel, III, Subramanian Ramesh, Robert C. Armstrong, Gary Scott Delp, Scott Allen Peterson
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Publication number: 20120012896Abstract: An improved integrated circuit cell architecture is provided for configurability between a memory cell or logic elements. The cell architecture is configured on variable layers above a first layer of metal, with the first layer of metal and layers therebelow reserved as fixed layers. By coupling a maximum of two layout cells together, a single-port or dual-port memory cell is realized. Likewise, by interconnecting transistors within a single cell or transistors among two or more cells, a logic device is realized. Within each cell, the bit lines are arranged on a layer separate from the wordlines, and extend orthogonal to each other.Type: ApplicationFiled: September 23, 2011Publication date: January 19, 2012Inventors: Ramnath Venkatraman, Carl Anthony Monzel, III, Subramanian Ramesh
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Patent number: 8044437Abstract: An improved integrated circuit cell architecture is provided for configurability between a memory cell or logic elements. The cell architecture is configured on variable layers above a first layer of metal, with the first layer of metal and layers therebelow reserved as fixed layers. By coupling a maximum of two layout cells together, a single-port or dual-port memory cell is realized. Likewise, by interconnecting transistors within a single cell or transistors among two or more cells, a logic device is realized. Within each cell, the bit lines are arranged on a layer separate from the wordlines, and extend orthogonal to each other.Type: GrantFiled: May 16, 2005Date of Patent: October 25, 2011Assignee: LSI Logic CorporationInventors: Ramnath Venkatraman, Carl Anthony Monzel, III, Subramanian Ramesh
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Patent number: 7404154Abstract: A basic cell circuit architecture having plurality of cells with fixed transistors configurable for the formation of logic devices and/or single/dual port memory devices within a structured ASIC is provided. Different configurations of ensuing integrated circuits are achieved by forming variable interconnect layers above the fixed structures. The circuit architecture can achieve interconnection of transistors within a single cell and/or across multiple cells. The interconnection can be configured to form basic logic gates as well as more complex digital and analog subsystems. In addition, each cell contains a layout of transistors that can be variably coupled to achieve a memory device, such as a SRAM device. By having the capability of forming either a logic circuit element, a memory device, or both, the circuit architecture is both memory-centric and logic-centric, and more fully adaptable to modern-day SoCs.Type: GrantFiled: July 25, 2005Date of Patent: July 22, 2008Assignee: LSI CorporationInventors: Ramnath Venkatraman, Michael N. Dillon, David A. Gardner, Carl Anthony Monzel, III, Subramanian Ramesh, Robert C. Armstrong, Gary Scott Delp, Scott Allen Peterson
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Patent number: 6982891Abstract: A re-configurable core cell is provided that can be used as either a content addressable memory cell or a dual-ported static read only memory cell. The re-configurable core cells are pre-diffused on the chip. The core cells may then be configured as CAM or SRAM with a metal layer. The peripheral logic of the CAM or SRAM may be built from gate array devices.Type: GrantFiled: June 10, 2003Date of Patent: January 3, 2006Assignee: LSI Logic CorporationInventor: Carl Anthony Monzel, III
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Patent number: 6864716Abstract: A pre-diffused high density array of core memory cells is provided in a metal programmable device. The peripheral logic is made up of gate array cells in the metal programmable device. The peripheral logic may be configured to access the core memory cells as various memory types, widths, depths, and other configurations. If the entire memory is not needed, then the unused memory cells can be used as logic gates. The application-specific circuit, including peripheral logic, memory interface logic, and memory configuration is programmed with a metal layer.Type: GrantFiled: June 9, 2003Date of Patent: March 8, 2005Assignee: LSI Logic CorporationInventors: Carl Anthony Monzel, III, Michael Dillon, Bret Alan Oeltjen
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Publication number: 20040246023Abstract: A pre-diffused high density array of core memory cells is provided in a metal programmable device. The peripheral logic is made up of gate array cells in the metal programmable device. The peripheral logic may be configured to access the core memory cells as various memory types, widths, depths, and other configurations. If the entire memory is not needed, then the unused memory cells can be used as logic gates. The application-specific circuit, including peripheral logic, memory interface logic, and memory configuration is programmed with a metal layer.Type: ApplicationFiled: June 9, 2003Publication date: December 9, 2004Inventors: Carl Anthony Monzel, Michael Dillon, Bret Alan Oeltjen