Abstract: Processing signals is disclosed. A method includes receiving a signal transmission with a nb/mb encoding scheme that maps n-bit words to m-bit symbols. In this scheme, m>n. The method further includes, for a first payload data word in the transmission, determining that the first payload data word corresponds to a valid payload data word, and as a result, assigning a first reliability metric to bits in the first payload data word. The method further includes for a second payload data word in the transmission, determining that the second payload data word does not correspond to a valid payload data word, and as a result, assigning a second reliability metric to bits in the second payload data word. The method further includes performing signal decoding using the assigned reliability metrics.

Abstract: Processing signals is disclosed. A method includes receiving a signal transmission with a nb/mb encoding scheme that maps n-bit words to m-bit symbols. In this scheme, m>n. The method further includes, for a first payload data word in the transmission, determining that the first payload data word corresponds to a valid payload data word, and as a result, assigning a first reliability metric to bits in the first payload data word. The method further includes for a second payload data word in the transmission, determining that the second payload data word does not correspond to a valid payload data word, and as a result, assigning a second reliability metric to bits in the second payload data word. The method further includes performing signal decoding using the assigned reliability metrics.

Abstract: Clock recovery from a serial data signal involves using a serializer/deserializer (SERDES) to produce a clock signal which periodically alternates between high and low output clock values. These high and low clock values are generated by outputting for each clock period a series of N digital bits including a plurality of low-level bits to form each low output clock value and a plurality of high-level bits to form each high output clock value. A sync pulse obtained from a sync word present in each frame of the serial data signal is used to periodically determine a frequency error of the clock signal. The frequency error is used as a basis to change a phase of the adjusted clock signal responsive to the frequency error.

Abstract: Systems and methods for synchronize word correlation. The methods comprise: obtaining first values that each indicate a likelihood or probability that a respective timeslot in a symbol timing window of a carrier wave is meant or expected to include energy; multiplying, by the correlator, the first values respectively by correlation coefficients to produce a plurality of products (wherein at least one of the correlation coefficients comprises a negative coefficient value); generating a correlation value by combining the products together; determining whether a synchronization word has been detected with a given amount of likelihood based on the correlation value; and causing symbol timing synchronization at a receiver when a determination is made that the synchronization word has been detected with the given amount of likelihood based on the correlation value.

Abstract: Systems and methods for integrating genomic results with electronic health records in accordance with embodiments of the invention are disclosed. In one embodiment, a method includes obtaining first raw genetic data formatted in a first format, obtaining second raw genetic data formatted in a second format normalizing the first raw genetic data by substituting at least one symbol in the first raw genetic data, normalizing the second raw genetic data, generating genetic data for the patient by modifying the first raw genetic data by converting the normalized symbols in the first raw genetic data to a common format, modifying the second raw genetic data by converting the normalized symbols in the second raw genetic data to the common format, and generating the genetic data for the patient based on the first raw genetic data and the second raw genetic data, and storing the genetic data.

Abstract: Systems and methods for synchronize word correlation. The methods comprise: obtaining first values that each indicate a likelihood or probability that a respective timeslot in a symbol timing window of a carrier wave is meant or expected to include energy; multiplying, by the correlator, the first values respectively by correlation coefficients to produce a plurality of products (wherein at least one of the correlation coefficients comprises a negative coefficient value); generating a correlation value by combining the products together; determining whether a synchronization word has been detected with a given amount of likelihood based on the correlation value; and causing symbol timing synchronization at a receiver when a determination is made that the synchronization word has been detected with the given amount of likelihood based on the correlation value.

Abstract: Clock recovery from a serial data signal involves using a serializer/deserializer (SERDES) to produce a clock signal which periodically alternates between high and low output clock values. These high and low clock values are generated by outputting for each clock period a series of N digital bits including a plurality of low-level bits to form each low output clock value and a plurality of high-level bits to form each high output clock value. A sync pulse obtained from a sync word present in each frame of the serial data signal is used to periodically determine a frequency error of the clock signal. The frequency error is used as a basis to change a phase of the adjusted clock signal responsive to the frequency error.

Abstract: Clock recovery from a serial data signal involves using a serializer/deserializer (SERDES) to produce a clock signal which periodically alternates between high and low output clock values. These high and low clock values are generated by outputting for each clock period a series of N digital bits including a plurality of low-level bits to form each low output clock value and a plurality of high-level bits to form each high output clock value. A sync pulse obtained from a sync word present in each frame of the serial data signal is used to periodically determine a frequency error of the clock signal. The frequency error is used as a basis to change a phase of the adjusted clock signal responsive to the frequency error.

Abstract: Systems and methods for operating a communication device. The methods comprise: receiving a carrier signal modulated with a modulation signal comprising a symbol conveyed in a symbol timing window; determining an energy value for each timeslot in the symbol timing window; combining the energy values to determine a combined energy value for each bit of the symbol in a manner in which the combined energy value is penalized if more than one timeslot of the symbol timing window comprises energy contained in the carrier signal; and generating a soft value for each bit of the sequence of bits by combining the combined energy value with a weight value, where the weight value is selected from a plurality of weight values based on a number of timeslots in the symbol timing window which comprises energy contained in the carrier signal.

Abstract: Synchronizing a pulse position modulation (PPM) signal. A method includes performing a first synchronization operation by receiving a first series of symbols. The symbols in the first series are transmitted with a pulse in a known slot, such that the symbols comprise pulses that are substantially equally spaced in time from adjacent symbols. The first synchronization operation includes identifying when each pulse is received for each of the symbols and using information identifying when each pulse is received for each of the symbols in the first series of symbols to identify symbol and slot boundaries for the pulse position modulation signal. The method further includes performing a second synchronization operation by receiving a second series of symbols transmitted in a known pattern, and identifying the known pattern in the received second series of symbols to identify a frame boundary.

Abstract: Methods and systems adapted for providing forward error correction for data packets containing a relationship between the data in each data packet. Data packets encoded in one error correction coding scheme are received and a second error correction coding scheme is identified based on the relationship between the data in each data packet. The data packets are then decoded using the second error correction coding scheme.

Abstract: Systems and methods for integrating genomic results with electronic health records in accordance with embodiments of the invention are disclosed. In one embodiment, a method includes obtaining first raw genetic data formatted in a first format, obtaining second raw genetic data formatted in a second format normalizing the first raw genetic data by substituting at least one symbol in the first raw genetic data, normalizing the second raw genetic data, generating genetic data for the patient by modifying the first raw genetic data by converting the normalized symbols in the first raw genetic data to a common format, modifying the second raw genetic data by converting the normalized symbols in the second raw genetic data to the common format, and generating the genetic data for the patient based on the first raw genetic data and the second raw genetic data, and storing the genetic data.

Abstract: Methods and systems adapted for providing forward error correction for data packets containing a relationship between the data in each data packet. Data packets encoded in one error correction coding scheme are received and a second error correction coding scheme is identified based on the relationship between the data in each data packet. The data packets are then decoded using the second error correction coding scheme.

Abstract: Detecting timing of a synchronization sequence included in a data stream transmitted in a noisy channel. The synchronization sequence is a known data sequence purposely injected into the data stream for synchronization. A data stream waveform, is obtained from a noisy communication channel. The data stream waveform includes an instance of a synchronization sequence waveform. One or more samples of the synchronization sequence waveform are obtained. One or more samples of a model synchronization sequence waveform are obtained. The model synchronization sequence waveform models an expected waveform for the synchronization sequence being transmitted on the communication channel by applying the synchronization sequence to a model of the communication channel.

Abstract: A return-to-zero control signal for controlling a modulator can be generated from two separate streams. A first data stream can include a pulse for each logical one that appears in an input data stream, while a second data stream can include a pulse for each logical zero that appears in the input data stream. The first and second data streams can be combined in a manner that yields the return-to-zero control signal. The first and second data streams can be generated in digital circuitry, such as an FPGA, to minimize the analog path for generating the return-to-zero control signal.

Abstract: There is provided a broadcast router that includes a plurality of input cards, a plurality of output cards, at least one programmable device, and a configuration control card. The plurality of input cards input data into the broadcast router. The plurality of output cards output the data from the broadcast router. The configuration control card stores configuration information for configuring the at least one programmable device to perform a first set of functions. The configuration control card is adapted for removal and replacement by at least one other configuration control card that stores other configuration information for configuring the at least one programmable device to perform a second set of functions having a difference from the first set of functions so as to change a functionality of the broadcast router.

Abstract: There is provided a broadcast router that includes a plurality of input cards (410), a plurality of output cards (460), at least one programmable device (466), and a configuration control card (498). The plurality of input cards input data into the broadcast router. The plurality of output cards output the data from the broadcast router. The configuration control card stores configuration information for configuring the at least one programmable device to perform a first set of functions. The configuration control card is adapted for removal and replacement by at least one other configuration control card that stores other configuration information for configuring the at least one programmable device to perform a second set of functions having a difference from the first set of functions so as to change a functionality of the broadcast router.

Abstract: There is provided a broadcast router that includes at least one chassis adapted for a first, a second, and a third configuration. The first configuration (401 A) includes a plurality of input cards and no output cards. The second configuration (401 B) includes a plurality of output cards and no input cards. The third configuration (400) includes a plurality of input and output cards.

Abstract: A router, for routing at least one input signal to at least one output, comprises at least one input module and at least one output module. Each of the input and output modules includes at least one clock selector circuit for selecting from among a first and second clock signal, and an oscillator signal, as a common output clock signal for the at least first router, based in part on whether at least one of the first and second clock signals has toggled. The clock selector circuit provides redundancy as well as distribution of clock signals among elements within each module.

Abstract: A fully redundant linearly expandable router is comprised of first, second, third and fourth router components. Each router component includes first and second routing engines. First, second and third discrete links couple the first routing engine to the first routing engines, respectively. Fourth and fifth discrete links couple the first routing engine to the first routing engines, respectively. A sixth discrete link couples the routing engine to the routing engine. Seventh, eighth and ninth discrete links couple the second routing engine to the second routing engines, respectively. Tenth and eleventh discrete links couple the second routing engine to the second routing engines, respectively. A twelfth discrete link couples the routing engine to the router engine.