Abstract: A frequency divider uses a single D flip-flop integrated circuit having an inverted output and an asynchronous clear input between which a feedback loop comprising a delay Tau is connected. The frequency divider receives a multi-GHz input frequency f.sub.1, and divides by any integer N to produce an output frequency f.sub.2 =f.sub.1 /N using the internal delay of the D flip-flop between input and output (CK-to-Q), and the internal delay between the asynchronous clear input to the output (CLR-to-Q). Solving for the amount of delay Tau in the feedback loop necessary to produce the desired integer, or divide ratio, N, according to a predetermined formula is also required. An integrated circuit D flip-flop manufactured by Gigabit Logic is preferably selected to provide the high input frequency capability, external to which is added the feedback loop for determining the divide ration desired. The divide ratio, or integer by which the input frequency is divided, includes the ability to divide by a non-2.sup.