Abstract: A secured subspace facility is provided for ensuring isolated storage for transactions running under an operating system main task. Isolation is achieved by attaching, from an operating system task, subtasks that will restrict application addressing. The attaching includes defining a subspace address environment as home space within a dispatchable unit access list (DU-AL) associated with each attached subtask. Multiple subtasks can be attached with each subtask running applications in an isolated address subspace, notwithstanding execution of the applications in address register addressing mode.

Abstract: Ensuring that a given transactional unit of work arrives at an appropriate server instance. A server instance receives a request that is associated with a unit of work. The server instance that received the request determines whether it is responsible for the unit of work associated with that request. When the server instance is responsible for the unit of work, the server instance processes the request. When the server instance is not responsible for the unit of work, it attempts to register its interest in the unit of work. If this attempt is successful, then the server instance can process the request. If the attempt is unsuccessful, then the responsible server instance is located and the request is forwarded to the responsible server instance.

Abstract: Distributed computing environment (DCE) remote procedure calls (RPCs) are integrated with an advisory work load manager (WLM) to provide a way to intelligently dispatch RPC requests among the available application server processes. The routing decisions are made dynamically (for each RPC) based on interactions between the location broker and an advisory work load manager. Furthermore, when the system contains multiple coupled processors (tightly coupled within a single frame, or loosely coupled within a computing complex, a local area network (LAN) configuration, a distributed computing environment (DCE) cell, etc.), the invention extends to balance the processing of RPC requests and the associated client sessions across the coupled systems. Once a session is assigned to a given process, the invention also supports performance monitoring and reporting, dynamic system resource allocation for the RPC requests, and potentially any other benefits that may be available through the specific work load manager (WLM).

Abstract: A method and system for providing a PROGRAM CALL to a dispatchable unit's base space is described herein. A program call to a dispatchable unit's (PC to DU) base space bit is added to each entry-table entry in order to determine whether a PROGRAM CALL to a base space is to be made. Should the bit indicate that a PROGRAM CALL to a dispatchable unit's base space is to be made, then in one embodiment, the base address space number-second-table entry origin (BASTEO) and base address space number (BASN) stored in the dispatchable unit control table (DUCT) are used in identifying the base space and accessing associated control information for the identified base space. In another embodiment, the BASN stored in the DUCT is used in ASN translation to identify the base space and access the associated control information for the base space.

Abstract: Provides a dynamic execution link between an analyzer program and each hook instruction in a program. Special types of hook instructions are provided for use in a hooked program. The link causes the analyzer program to execute as part of a continuous uninterrupted execution for each hook instruction. The link uses hardware and/or internal code to access a hook control area which provides linkage information needed to invoke the execution of the analyzer program upon completion of the hook instruction and to continue the execution of the hooked program following the completion of the analyzer program. The linkage information includes the entry location into the analyzer program, and also locates the first hook work area (HWA) of a sequence of HWAs, from which an HWA is assigned to each current hook instruction. The assigned HWA stores a return point location in the hooked program at an instruction following the current hook instruction.

Abstract: A Branch in Subspace Group (BSG) instruction is executed in problem state (for example by an application program) for providing a fast instruction branch between address spaces within a restricted group of address spaces called a subspace group. The subspace group contains two types of address spaces: a base space and any number of subspaces. The subspace group is set up in a control table associated with each dispatchable unit (DU). This DU control table contains: an identifier of a base space, an identifier of an access list that contains identifiers of all subspaces in the subspace group, an indicator of whether CPU control was last given to a subspace or to the base space, and an identifier of a last entered subspace in the group. The BSG instruction has an operand defining a general register containing the target virtual address and an associated access register containing an access-list-entry token (ALET) defining the target address space.

Abstract: An application, executing on a first processing element in a MP system without an asymmetric feature, issues an instruction requiring that feature to complete. A program check interruption gives control to interrupt handlers, which create a high-priority, non-preemptable work unit control block and enters the dispatcher to enqueue the work unit on a processor-related queue associated with a second processing element having the asymmetric feature. When the dispatcher executes in the second processing element, it executes the non-preemptable work unit, which transfers control to the application at the point of interruption. Subsequently the application has only whatever processor affinity obtained prior to the program check.

Abstract: Provides three access levels of storage key protection, comprising a supervisory level (key 0), an intermediate level of non-public and non-supervisory keys (keys 1-8, 10-15), and an unique public level (key 9). The program routines operating with a supervisory-level access key can access both the public level and the intermediate level of storage blocks. Although a program routine operating with an access key in the intermediary access level cannot access any supervisory level storage block, it can access any block assigned a public level storage key, as well as any storage block assigned the respective intermediate level key. One or more third-level public storage keys (PSKs) may be provided. A program access key using one of the PSK values can only access blocks having the same PSK value, and it cannot access blocks having any other key value.

Abstract: A program authorization mechanism for authorizing access to an address space in the main memory of a computer system by a program being run under a multiple address space facility. An access-list entry is associated with each address space, each access-list entry being designated by an access-list-entry token contained in an access register. Each access-list entry includes a private indicator which indicates if the associated address space can be accessed by all programs from this access-list entry or if the associated address space can only be accessed by an authorized program. For program to be authorized, an extended authorization index in a control register must match an access-list extended authorization index in the access-list entry, or the extended authorization index value must be authorized in an authority table associated with the address space. An instruction for testing a given extended authorization index for a given access-list-entry is also disclosed.

Abstract: A method and apparatus is provided to translate the contents of access registers into information for use in performing addressing functions for multiple virtual address spaces. The access registers represent the full addressing capability of the system but do not directly contain the addressing information. The system has a plurality of general purpose registers, a plurality of access registers associated with the general registers, an access list having access list entries which is addressed by the contents of the access register, memory storage for holding address space number second table entries (ASTE), where the contents of the access list entry locate the ASTE and where the ASTE contains the addressing information needed to translate a virtual address when combined with the contents of a general purpose register. Access register translation (ART) consists of the process of determining addressing information by using the access list entry and the ASTE.

Abstract: The embodiment enables multiple virtual data domains to be accessible to a program executing on a processor. A data domain is a set of virtual address spaces for containing data that can be accessed by an executing program. Two types of data domains are defined by access lists, called PSAL and DUAL. Each list has entries specifying virtual address spaces accessible to an executing program. The program is located in a program address space. The program address space and each data domain are located through respective control registers. On a program call, the processor loads a control register with means to identify the PSAL data domain. The loaded control register provides the called program with immediate access to its own PSAL data domain. When the call is from a different program address space, the calling program space's PSAL data domain immediately becomes non-accessible due to overlaying in the single loading of the one control register.

Abstract: The creation of address spaces that need not map in their address range all of the routines of the operating system basic control program (BCP) is provided. The BCP, though, will have easy access to (addressability of) the home address space, i.e. to the virtually mapped and addressable control blocks therein. Addressability can be switched from a previously dispatched address space to the home address space. The dispatcher becomes capable of addressing the home address space when predetermined bits in a program status word are set. Once the home address space becomes addressable, the BCP is now capable of easily accessing control blocks in the home address space without the need to modify CPU status or pointers to any other address spaces. If pointers to any other address space are modified, current address translation in the home address space would not be affected. Providing access to the home address space increases performance and reduces complexity.

Abstract: The embodiment provides selective supervisory disablement of fetch protection for a special storage subarea (such as for the first half of the first 4KB block) while fetch protection is enabled for an area containing the subarea by a single storage protect key. That is, the fetch protect for the subarea (normally provided in the fetch protect for the entire area) by the area's protect key is overriden by the selective subarea disablement control, so that accesses to the subarea are not fetch protected by the storage key. The override protection control is secured by its enablement via a field position in a control register only accessible to supervisory programming. Thus, while fetch protection is set on for a predefined 4KB block, the fetch protect override controls can disable the fetch protection for a portion of the block's real addresses (e.g. addresses 0-2047).