Abstract: A method, performed by a processor, of determining a square root using a single processor cycle per iteration is described. The method includes, in a single cycle: obtaining, from a stored lookup table, a quotient digit and a square of the quotient digit; retrieving a current solution; and determining a new solution using the current solution and the quotient digit. Circuitry configured to perform the method is described.

Abstract: A method, performed by a processor, of determining a square root using a single processor cycle per iteration is described. The method includes, in a single cycle: obtaining, from a stored lookup table, a quotient digit and a square of the quotient digit; retrieving a current solution; and determining a new solution using the current solution and the quotient digit. Circuitry configured to perform the method is described.

Abstract: A multiplier (12) is disclosed that includes an encoder (36), a hierarchy of compressors (40, 42, 44, 50, 52, 60 and 70), a bit detector (130) and a switch (134). The encoder (36) is operable to receive a first and second encoder input. The compressors (40, 42, 44, 50, 52, 60 and 70) are coupled to the encoder (36). The compressors (40,42, 44, 50, 52, 60 and 70) are operable to receive a first number of inputs and to generate a second number of outputs, with the second number being less than the first number. The bit detector (130) is operable to monitor the first encoder input to determine whether the first encoder input is in a reduced precision range (28). The bit detector (130) is also operable to deactivate a subset of the compressors (40 and 50) when the bit detector (130) determines that the first encoder input is in the reduced precision range (28). The switch (134) is coupled to a specified one of the compressors (42).

Abstract: In a multiplier unit having a preprocessor stage, a multiplier stage, and a summation stage, the multiplier stage includes a shift register, a gate component for controllably transmitting the multiplicand A in a manner determined by a bit signal of multiplier B applied to the gate component control terminal. Partial products are grouped by multiplicand digits and each digit is applied, through delay components determined by the order of the digit, to first terminals of an associated adder components. Output signals from each adder component is transmitted through a plurality of delay components and applied to second input terminals of the same adder component. In this manner, partial products A.sub.p *B.sub.q are assembled and the partial products (A.sub.0 + . . . A.sub.M)*B.sub.q =A*B.sub.q can be applied to the summation unit in a single period. When the multiplier is an integer multiple of the multiplicand, the implementation is particularly convenient.

Abstract: A multiplier and method of multiplying a multiplicand by a multiplier comprising providing a multiplicand of predetermined radix, preferably two, and a predetermined multiple of the multiplicand, preferably three, of the predetermined radix. First and second paths are provided, each path including the multiplicand and the multiple of the multiplicand. One of the multiplicand or multiple of the multiplicand in said first path is selected responsive to the value of the multiplier and one of the multiplicand or multiple of the multiplicand in the second path is selected responsive to the value of the multiplier. The selected multiplicand or multiple of the multiplicand in said first path is left shifted a number of shifts determined by the value of the multiplier and the selected multiplicand or multiple of the multiplicand in the second path is left shifted a number of shifts determined by the value of the multiplier.