Patents by Inventor Carl E. Love
Carl E. Love has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9298651Abstract: In-memory accumulation of hardware counts in a computer system is carried out by continuously sending count values from full-speed hardware counter units to a memory controller. A sending unit periodically samples performance data from the hardware counter units, and transmits count values to a bus interface for an interconnection bus which communicates with the memory controller. The memory controller responsively updates an accumulated count value stored in system memory using the current count value, e.g., incrementing the accumulated count value. A count value can be sent with a pointer to a memory location and an instruction on how the location is to be updated. The instruction may be an atomic read-modify-write operation, and the memory controller can include a dedicated arithmetic logic unit to carry out that operation. A data harvester can then be used to harvest accumulated count values by reading them from a table in system memory.Type: GrantFiled: June 24, 2013Date of Patent: March 29, 2016Assignee: International Business Machines CorporationInventors: Peter J. Heyrman, Venkat R. Indukuru, Carl E. Love, Aaron C. Sawdey, Philip L. Vitale
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Publication number: 20140379953Abstract: In-memory accumulation of hardware counts in a computer system is carried out by continuously sending count values from full-speed hardware counter units to a memory controller. A sending unit periodically samples performance data from the hardware counter units, and transmits count values to a bus interface for an interconnection bus which communicates with the memory controller. The memory controller responsively updates an accumulated count value stored in system memory using the current count value, e.g., incrementing the accumulated count value. A count value can be sent with a pointer to a memory location and an instruction on how the location is to be updated. The instruction may be an atomic read-modify-write operation, and the memory controller can include a dedicated arithmetic logic unit to carry out that operation. A data harvester can then be used to harvest accumulated count values by reading them from a table in system memory.Type: ApplicationFiled: June 24, 2013Publication date: December 25, 2014Inventors: Peter J. Heyrman, Venkat R. Indukuru, Carl E. Love, Aaron C. Sawdey, Philip L. Vitale
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Patent number: 7984222Abstract: Systems for providing performance monitoring in a memory system. The memory system includes a memory controller, a plurality of memory devices, a memory bus and a memory hub device. The memory controller receives and responds to memory access requests. The memory bus is in communication with the memory controller. The memory hub device is in communication with the memory bus. The memory hub device includes a memory interface for transferring one or more of address, control and data information between the memory hub device and the memory controller via the memory bus. The memory hub device also includes a memory device interface for communicating with the memory devices. The memory hub device further includes a performance monitor for monitoring and reporting one or more of memory bus utilization, memory device utilization, and performance characteristics over defined intervals during system operation.Type: GrantFiled: January 13, 2009Date of Patent: July 19, 2011Assignee: International Business Machines CorporationInventors: Kevin C. Gower, Carl E. Love, Dustin J. VanStee
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Patent number: 7861126Abstract: An implementation-efficient, multiple-counter value hardware performance counter is disclosed. A hardware counter of one embodiment includes a memory array and a hardware incrementer. The array stores counter values that are indexable by an index constructed based at least on the number of events to which the counter values correspond. The index may be constructed as a concatenation of a number of bits binarily representing the number of events, and a number of bits binarily representing the number of qualifiers to the events. The incrementer reads the counter values from the array, increments the counter values, and writes the resulting counter values back into the array. The array may be divided into banks over which the counter values are stored, where each bank has a separate instance of the incrementer. Each bank may have a separate instance of the index that indexes only those counters stored in the bank.Type: GrantFiled: June 29, 2008Date of Patent: December 28, 2010Assignee: International Business Machines CorporationInventors: Carl E. Love, Donald R. DeSota, Jaeheon Jeong, Russell M. Clapp
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Publication number: 20090119466Abstract: Systems for providing performance monitoring in a memory system. The memory system includes a memory controller, a plurality of memory devices, a memory bus and a memory hub device. The memory controller receives and responds to memory access requests. The memory bus is in communication with the memory controller. The memory hub device is in communication with the memory bus. The memory hub device includes a memory interface for transferring one or more of address, control and data information between the memory hub device and the memory controller via the memory bus. The memory hub device also includes a memory device interface for communicating with the memory devices. The memory hub device further includes a performance monitor for monitoring and reporting one or more of memory bus utilization, memory device utilization, and performance characteristics over defined intervals during system operation.Type: ApplicationFiled: January 13, 2009Publication date: May 7, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kevin C. Gower, Carl E. Love, Dustin J. VanStee
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Patent number: 7493439Abstract: Systems and methods for providing performance monitoring in a memory system. Embodiments include a memory system for storing and retrieving data for a processing system. The memory system includes a memory controller, a plurality of memory devices, a memory bus and a memory hub device. The memory controller receives and responds to memory access requests. The memory bus is in communication with the memory controller. The memory hub device is in communication with the memory bus. The memory hub device includes a memory interface for transferring one or more of address, control and data information between the memory hub device and the memory controller via the memory bus. The memory hub device also includes a memory device interface for communicating with the memory devices. The memory hub device further includes a performance monitor for monitoring and reporting one or more of memory bus utilization, memory device utilization, and performance characteristics over defined intervals during system operation.Type: GrantFiled: August 1, 2006Date of Patent: February 17, 2009Assignee: International Business Machines CorporationInventors: Kevin C. Gower, Carl E. Love, Dustin J. VanStee
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Publication number: 20080263263Abstract: An implementation-efficient, multiple-counter value hardware performance counter is disclosed. A hardware counter of one embodiment includes a memory array and a hardware incrementer. The array stores counter values that are indexable by an index constructed based at least on the number of events to which the counter values correspond. The index may be constructed as a concatenation of a number of bits binarily representing the number of events, and a number of bits binarily representing the number of qualifiers to the events. The incrementer reads the counter values from the array, increments the counter values, and writes the resulting counter values back into the array. The array may be divided into banks over which the counter values are stored, where each bank has a separate instance of the incrementer. Each bank may have a separate instance of the index that indexes only those counters stored in the bank.Type: ApplicationFiled: June 29, 2008Publication date: October 23, 2008Inventors: Carl E. Love, Donald R. DeSota, Jaeheon Jeong, Russell M. Clapp
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Patent number: 7437622Abstract: An implementation-efficient, multiple-counter value hardware performance counter is disclosed. A hardware counter of one embodiment includes a memory array and a hardware incrementer. The array stores counter values that are indexable by an index constructed based at least on the number of events to which the counter values correspond. The index may be constructed as a concatenation of a number of bits binarily representing the number of events, and a number of bits binarily representing the number of qualifiers to the events. The incrementer reads the counter values from the array, increments the counter values, and writes the resulting counter values back into the array. The array may be divided into banks over which the counter values are stored, where each bank has a separate instance of the incrementer. Each bank may have a separate instance of the index that indexes only those counters stored in the bank.Type: GrantFiled: April 22, 2007Date of Patent: October 14, 2008Assignee: International Business Machines CorporationInventors: Carl E. Love, Donald R. DeSota, Jaeheon Jeong, Russell M. Clapp
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Publication number: 20080034148Abstract: Systems and methods for providing performance monitoring in a memory system. Embodiments include a memory system for storing and retrieving data for a processing system. The memory system includes a memory controller, a plurality of memory devices, a memory bus and a memory hub device. The memory controller receives and responds to memory access requests. The memory bus is in communication with the memory controller. The memory hub device is in communication with the memory bus. The memory hub device includes a memory interface for transferring one or more of address, control and data information between the memory hub device and the memory controller via the memory bus. The memory hub device also includes a memory device interface for communicating with the memory devices. The memory hub device further includes a performance monitor for monitoring and reporting one or more of memory bus utilization, memory device utilization, and performance characteristics over defined intervals during system operation.Type: ApplicationFiled: August 1, 2006Publication date: February 7, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kevin C. Gower, Carl E. Love, Dustin J. VanStee
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Patent number: 7272754Abstract: An implementation-efficient, multiple-counter value hardware performance counter is disclosed. A hardware counter of one embodiment includes a memory array and a hardware incrementer. The array stores counter values that are indexable by an index constructed based at least on the number of events to which the counter values correspond. The index may be constructed as a concatenation of a number of bits binarily representing the number of events, and a number of bits binarily representing the number of qualifiers to the events. The incrementer reads the counter values from the array, increments the counter values, and writes the resulting counter values back into the array. The array may be divided into banks over which the counter values are stored, where each bank has a separate instance of the incrementer. Each bank may have a separate instance of the index that indexes only those counters stored in the bank.Type: GrantFiled: September 27, 2003Date of Patent: September 18, 2007Assignee: International Business Machines CorporationInventors: Carl E. Love, Donald R. DeSota, Jaeheon Jeong, Russell M. Clapp
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Patent number: 6848026Abstract: Caching memory contents into cache partitions based on their locations is disclosed. A location of a line of memory to be cached in a cache is determined. The cache is partitioned into a number of cache sections. The section for the line of memory is determined based on the location of the line of memory as applied against a memory line location-dependent allocation policy. The line of memory is then stored in the section of the cache determined.Type: GrantFiled: November 9, 2001Date of Patent: January 25, 2005Assignee: International Business Machines CorporationInventors: Donald R. DeSota, Adrian C. Moga, Carl E. Love, Russell M. Clapp
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Publication number: 20030093622Abstract: Caching memory contents into cache partitions based on their locations is disclosed. A location of a line of memory to be cached in a cache is determined. The cache is partitioned into a number of cache sections. The section for the line of memory is determined based on the location of the line of memory as applied against a memory line location-dependent allocation policy. The line of memory is then stored in the section of the cache determined.Type: ApplicationFiled: November 9, 2001Publication date: May 15, 2003Applicant: International Business Machines CorporationInventors: Donald R. Desota, Adrian C. Moga, Carl E. Love, Russell M. Clapp