Abstract: A wireless transceiver including an oscillator, a radio, a baseband processor and MAC device that performs apiori frequency offset correction. The radio converts between RF signals and baseband signals. The baseband processor includes a frequency correction loop, an inverter and a combiner. The frequency correction loop generates a frequency offset signal based on a frequency difference between an oscillator reference frequency and frequency of a received signal. The inverter inverts the frequency offset signal and the combiner adjusts frequency of a transmit signal by the inverted frequency offset signal. The MAC processes received packets, identifies packets received from an AP, provides packets to the baseband processor for transmission, and controls the baseband processor to adjust transmit signals to a frequency of the AP. The baseband processor may include a memory or filter to store or update frequency offset values.

Abstract: The performance of a RAKE receiver for indoor multipath WLAN applications on direct sequence spread spectrum signals having relatively short codeword lengths is enhanced by embedding a decision feedback equalizer structure in the signal processing path through the receiver's channel matched filter and codeword correlator. The decision feedback equalizer serves to cancel both inter-codeword interference (ISI) or “bleed-over” between codewords, and intra-codeword chip interference (ICI) or smearing of the energy within the chips of a respective codeword.

Abstract: An FEC scheme for wireless receivers including a symbol detector, a symbol selector, CRC logic and output logic. The detector correlates each digital group of the packet with a symbol family and provides possible symbols and corresponding correlation factors. The selector selects several possible symbols for each digital group having the highest correlation factors. The CRC logic calculates possible CRC values for the packet using combinations of the selected symbols. The output logic evaluates the possible CRC values to determine whether there is a correct symbol combination. The system may include logic that determines a symbol quality (SQ) metric for each digital group based on a difference between the two highest correlation factors. The system may include a rank value filter that selects a predetermined number of second choice symbols based on the SQ metrics. The CRC logic calculates the CRC values using combinations of first and second choice symbols.

Abstract: A wireless transceiver including an oscillator, a radio, a baseband processor and MAC device that performs apiori frequency offset correction. The radio converts between RF signals and baseband signals. The baseband processor includes a frequency correction loop, an inverter and a combiner. The frequency correction loop generates a frequency offset signal based on a frequency difference between an oscillator reference frequency and frequency of a received signal. The inverter inverts the frequency offset signal and the combiner adjusts frequency of a transmit signal by the inverted frequency offset signal. The MAC processes received packets, identifies packets received from an AP, provides packets to the baseband processor for transmission, and controls the baseband processor to adjust transmit signals to a frequency of the AP. The baseband processor may include a memory or filter to store or update frequency offset values.

Abstract: The performance of a RAKE receiver for indoor multipath WLAN applications on direct sequence spread spectrum signals having relatively short codeword lengths is enhanced by embedding a decision feedback equalizer structure in the signal processing path through the receiver's channel matched filter and codeword correlator. The decision feedback equalizer serves to cancel both inter-codeword interference (ISI) or “bleed-over” between codewords, and intra-codeword chip interference (ICI) or smearing of the energy within the chips of a respective codeword.

Abstract: The performance of a RAKE receiver for indoor multipath WLAN applications on direct sequence spread spectrum signals having relatively short codeword lengths is enhanced by embedding a decision feedback equalizer structure in the signal processing path through the receiver's channel matched filter and codeword correlator. The decision feedback equalizer serves to cancel both inter-codeword interference (ISI) or ‘bleed-over’ between codewords, and intra-codeword chip interference (ICI) or smearing of the energy within the chips of a respective codeword.

Abstract: In a direct sequence spread spectrum receiver, an apparatus for obtaining and adjusting bit synchronization. In one aspect, the bit synchronization is adjusted by selectively inverting a clocking circuit to delay sampling by one-half a clock cycle and to combine the inversion with a skipping of one cycle to advance the sampling by one-half cycle. In another aspect of the invention, the synchronization circuit avoids overflow of accumulating components by downshifting both the partial sums and the input data when needed.

Abstract: Identification and extraction of hybrid, frequency-hopped direct sequence pseudo noise (FH/DS), signals from a multiband signal environment is effected by a sequential signal processing technique which examines the distribution of the energy content within a prescribed sub-spectrum window that is iteratively scanned or `slides` across the overall signal spectrum of interest. Based upon this energy content distribution, in particular the extent to which a sub-spectrum window contains energy that exhibits significant conjugate phase symmetry associated with a direct spread signal, the inventive signal processing technique proceeds to emphasize the spectral composition of components of which hybrid signals are comprised and to deemphasize the spectral composition of signals other than those contained in hybrid signals. Potential hybrid signal candidates whose spectral composition has been emphasized are then selectively combined with the deemphasized signals to isolate and identify the hybrid signals.

Abstract: A low probability of intercept communication system (CCSK)--modulates information signals onto an inverse fast Fourier transformation of a large number of simultaneous frequencies that have been determined to be reasonably `quiet` within a given system bandwidth, so as to produce a time domain pulse waveform. The amplitude of each transmitted frequency is weighted. Within the receiver equipment of each participant in the system, the incoming pulse waveform produced by the inverse fast Fourier transformation mechanism at the source is coupled to a fast Fourier transform operator, so as to separate the time domain signal into a plurality of frequency components that contain the modulated data. These components are then convolved with a replica of the plurality of quiet channels to derive a time domain output waveform from which the data modulation can be identified and recovered.

Abstract: In a spread spectrum communications system employing cyclic code shift keying as its primary modulation, the transmission waveform is spread for transmission security by modulo-2 adding a pseudo-noise sequence to the CCSK data symbols prior to phase modulating onto a carrier signal for transmission. If the transmission modulation is minimum shift keying (MSK) the two components of the data stream are applied to the carrier with a differential encoding step implicit in the modulation scheme. This differential encoding characteristic makes stripping of the PN spread function prior to CCSK demodulation difficult at the receiving end. In order to demodulate this waveform in an optimum manner, an array correlator, the adjacent correlator stages of which have one chip relative time displacements of their CCSK reference waveform, is employed. In effect the array correlator becomes a parallel array of matched filters matched to each cyclic shift of the incoming waveform.

Abstract: A detector (20) is provided for use in a communication receiver where a received spread spectrum data signal is detected using a locally generated reference signal to decode the data signal. The detector (20) includes first (22) and second channels (24) and circuitry (90) for applying the received encoded data signal to the first (22) and second channels (24). A local generator (50) is provided for generating the reference signal wherein the reference signal has polarity transitions. A demodulator (40) is included in the first channel (22) for generating a detected recovered data signal from the received data signal in response to the reference signal. Circuitry (52) is provided for detecting the polarity transitions in the reference signal and for generating a differential PN signal. Circuitry (42) is further provided in the second channel (24) for correlating the received data signal and the differential PN signal to thereby generate a recovered error signal.

Abstract: A method and apparatus is disclosed for decoding a redundantly coded digital signal wherein each information character is coded with a plurality of signal elements. Each of the signal elements is sampled by an analog to digital converter (110) and the resulting sample value is transmitted to an adder (114). The sampled value is added to an accumulated sum which is received from a storage circuit (128). The sum of the sampled value and the accumulated sum is transmitted through a selector switch (120) to both a decision circuit (126) and the storage circuit (128). After the last of the redundantly coded signal elements is sampled and the sampled values included within the accumulation sum, the state of the information character is determined by the decision circuit (126). Switch (120) then enters a null data set to reset the accumulated sum to zero for processing the next group of redundantly coded signal elements.

Abstract: A method and apparatus for phase modulating a carrier signal to convey an information signal (12) such that the carrier signal has a constant amplitude envelope. A Hilbert transform signal (14) of the information signal (12) is produced. The signals (12, 14) are sampled to produce signals (16, 18), which represent cartesian coordinate values. The cartesian coordinate values are then converted into equivalent polar vectors (20-36) which have both an amplitude (R) and an angle (.theta.). The polar vector quantity (R, .theta.) is converted into two unity amplitude vectors (A, B). The unity amplitude vectors (A, B) are offset from the polar vector quantity by an angle the cosine of which is proportional to the amplitude of the polar vector (R). The carrier signal is sequentially phase modulated phase angles of the unity amplitude vectors (A, B) for each sample period of the information signal.

Abstract: A method and apparatus for phase modulating a carrier signal to convey an information signal (12) such that the carrier signal has a constant amplitude envelope. A Hilbert transform signal (14) of the information signal (12) is produced. The signals (12, 14) are sampled to produce signals (16, 18), which represent cartesian coordinate values. The cartesian coordinate values are then converted into equivalent polar vectors (20-36) which have both an amplitude (R) and an angle (.theta.). The polar vector quantity (R,.theta.) is converted into two unity amplitude vectors (A, B). The unity amplitude vectors (A, B) are offset from the polar vector quantity by an angle the cosine of which is proportional to the amplitude of the polar vector (R). The carrier signal is sequentially phase modulated by each of the angles of the unity amplitude vectors (A, B) for each sample period of the information signal.

Abstract: A transversal correlator is disclosed for demodulating a phase shift keyed (PSK) signal. The PSK signal is mixed with a local oscillator signal to produce quadrature I-channel and Q-channel signals. The I-channel and Q-channel signals are sampled at a periodic rate and the samples are propagated through a shift register for each channel. A preselected pseudo noise signal is stored in a local register which has an output tap for each stage. Each of the analog shift registers has a stage corresponding to one of the stages of the local register. Each of the I-channel and Q-channel samples is multiplied by the binary state in the corresponding stage of the local register. This multiplying operation produces a plurality of product signals. Product signals for alternate samples of the I-channel signal are summed with alternate but offset samples of the Q-channel signal to produce a first summation signal.

Abstract: A recovery loop includes an analog circuit that mixes a fixed frequency signal from a temperature controlled oscillator (20) with an IF input to produce product signals corresponding to the quadrature components of data signals with frequency offset. A digital complex multiplier (32) is responsive to the product signals and to the output of a number controlled oscillator (34) to produce a digital output corresponding to the data signals. The output of the number controlled oscillator (34) is controlled by a digital phase lock loop.

Abstract: Three sample and hold circuits (26, 30 and 34) sample a received pulse amplitude modulated signal at twice the data bit frequency or timing of the received signal. The clock to the sample and hold circuits is timed so that three consecutive samples, two mid-bit samples and a transition sample are held in the circuits (26, 30 and 34) once every two sample periods. The mid-bit samples are added together by an adder (32) and divided by two in a divider (38) to provide an average. The transition sample is subtracted from this average in a subtractor (36) to produce an error signal. The error signal is normalized in a multiplier (44) using the reciprocal of the difference in magnitude between the two mid-bit samples to produce a normalized signal. A clock signal is generated by a voltage controlled oscillator (52) in response to the normalized signal at twice the bit frequency or bit timing and in synchronism therewith.

Abstract: A phase lock loop (10) includes a frequency and phase preset network for presetting a local oscillator (20) in substantial synchronism with a carrier signal. The preset network utilizes time delayed output signals from split or double correlators (32, 34, 36, 38) to determine a change in the phase angle between the local oscillator signal and the carrier signal for a known time period to determine the frequency of the local oscillator signal relative to the carrier signal frequency. The preset network determines the phase of the local oscillator signal relative to the carrier signal phase utilizing the summed output of one split correlator (32 and 34) and of another split correlator (36 and 38).

Abstract: A direct current responsive mixing circuit (10) includes three mixers (14, 16 & 18), each having one D.C. port and two A.C. ports. The D.C. ports are responsive to D.C. and A.C. signals, while the A.C. ports are responsive only to A.C. signals. One mixer (14) has an A.C. port (24) receiving a pump signal and a D.C. port (28) receiving an I input signal. A second mixer (16) has an A.C. port (26) receiving the pump signal and a D.C. port (32) receiving a Q input signal. The remaining A.C. ports of the first two mixers (14 and 16) are connected to the two A.C. ports (36 and 38) of the third mixer (18). An output signal having a component corresponding to the product of the I and Q input signals is produced at the D.C. port (40) of the third mixer (18). In this construction, the mixing circuit 10 is responsive to A.C. and D.C. input signals and may produce a D.C. output signal component.

Abstract: A spread spectrum radio transceiver includes a high data rate baseband processor and a radio circuit connected thereto. The baseband processor preferably includes a modulator for spread spectrum phase shift keying (PSK) modulating information for transmission via the radio circuit. The modulator may include at least one modified Walsh code function encoder for encoding information according to a modified Walsh code for substantially reducing an average DC signal component to thereby enhance overall system performance when AC-coupling the received signal through at least one analog-to-digital converter to the demodulator. The demodulator is for spread spectrum PSK demodulating information received from the radio circuit. The modulator and demodulator are each preferably operable in one of a bi-phase PSK (BPSK) mode at a first data rate and a quadrature PSK (QPSK) mode at a second data rate. These formats may also be switched on-the-fly in the demodulator. Method aspects are also disclosed.