Patents by Inventor Carl F. Barnhart
Carl F. Barnhart has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7478301Abstract: An integrated circuit and method of testing and repairing the integrated circuit. The integrated circuit includes: a multiplicity of macro-circuits having the same function; a fuse bank, the state of the fuses storing test data indicating at least which macro-circuits failed a test; and means for preventing utilization of failing macro-circuits during operation of the integrated circuit and a method generating a partial good integrated circuit, the method including: providing an integrated circuit have a multiplicity of macro-circuits arranged in one or more groups, each macro-circuit having the same function and a fuse bank containing fuses; testing each macro-circuit prior to a fuse programming operation; programming the fuses in the fuse bank in order to store data indicating at least which macro-circuits failed the testing step; and preventing utilization of each failing macro-circuit during operation of the integrated based on the data stored in the fuse bank.Type: GrantFiled: May 2, 2008Date of Patent: January 13, 2009Assignee: International Business Machines CorporationInventors: Leonard O. Farnsworth, III, Michael Z. Felske, Pamela S. Gillis, Benjamin P. Lynch, Michael R. Ouellette, Thomas St. Pierre, Tad J. Wilder, Carl F. Barnhart
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Patent number: 7434129Abstract: An integrated circuit and method of testing and repairing the integrated circuit. The integrated circuit includes: a multiplicity of macro-circuits having the same function; a fuse bank, the state of the fuses storing test data indicating at least which macro-circuits failed a test; and means for preventing utilization of failing macro-circuits during operation of the integrated circuit and a method generating a partial good integrated circuit, the method including: providing an integrated circuit have a multiplicity of macro-circuits arranged in one or more groups, each macro-circuit having the same function and a fuse bank containing fuses; testing each macro-circuit prior to a fuse programming operation; programming the fuses in the fuse bank in order to store data indicating at least which macro-circuits failed the testing step; and preventing utilization of each failing macro-circuit during operation of the integrated based on the data stored in the fuse bank.Type: GrantFiled: September 24, 2007Date of Patent: October 7, 2008Assignee: International Business Machines CorporationInventors: Leonard O. Farnsworth, III, Michael Z. Felske, Pamela S. Gillia, Benjamin P. Lynch, Michael R. Ouellette, Thomas St. Pierre, Tad J. Wilder, Carl F. Barnhart
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Publication number: 20080209289Abstract: An integrated circuit and method of testing and repairing the integrated circuit. The integrated circuit includes: a multiplicity of macro-circuits having the same function; a fuse bank, the state of the fuses storing test data indicating at least which macro-circuits failed a test; and means for preventing utilization of failing macro-circuits during operation of the integrated circuit and a method generating a partial good integrated circuit, the method including: providing an integrated circuit have a multiplicity of macro-circuits arranged in one or more groups, each macro-circuit having the same function and a fuse bank containing fuses; testing each macro-circuit prior to a fuse programming operation; programming the fuses in the fuse bank in order to store data indicating at least which macro-circuits failed the testing step; and preventing utilization of each failing macro-circuit during operation of the integrated based on the data stored in the fuse bank.Type: ApplicationFiled: May 2, 2008Publication date: August 28, 2008Inventors: Leonard O. Farnsworth, Michael Z. Felske, Pamela S. Gillis, Benjamin P. Lynch, Michael R. Ouellette, Thomas St. Pierre, Tad J. Wilder, Carl F. Barnhart
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Patent number: 7305600Abstract: An integrated circuit, including: a multiplicity of macro-circuits, each macro-circuit having the same function; a fuse bank containing a multiplicity of fuses, the state of the fuses storing test data indicating at least which macro-circuits failed a test; and means for preventing utilization of failing macro-circuits during operation of the integrated circuit and a method generating a partial good integrated circuit, the method including: providing an integrated circuit have a multiplicity of macro-circuits arranged in one or more groups, each macro-circuit having the same function and a fuse bank containing fuses; testing each macro-circuit prior to a fuse programming operation; programming the fuses in the fuse bank in order to store data indicating at least which macro-circuits failed the testing step; and preventing utilization of each failing macro-circuit during operation of the integrated based on the data stored in the fuse bank.Type: GrantFiled: August 29, 2003Date of Patent: December 4, 2007Assignee: International Business Machines CorporationInventors: Leonard O. Farnsworth, III, Michael Z. Felske, Pamela S. Gillis, Benjamin P. Lynch, Michael R. Ouellette, Thomas St.Pierre, Tad J. Wilder, Carl F. Barnhart
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Patent number: 6804803Abstract: A method of testing a circuit having multiple elements is disclosed. A plurality of faults representing the elements of the circuit for testing said circuit is created. The faults are grouped based on common attributes of the faults. A test pattern for each group of faults is created. Finally, the circuit is tested using test patterns for each group of faults.Type: GrantFiled: April 5, 2001Date of Patent: October 12, 2004Assignee: International Business Machines CorporationInventors: Carl F. Barnhart, Robert W. Bassett, Brion L. Keller, David E. Lackey, Mark R. Taylor, Donald L. Wheater
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Patent number: 6795944Abstract: The test generation software takes advantage of the regularity of the structure without introducing significant changes to the test pattern generation software or to the manufacturing test tools. In this manner, the number of test patterns, the pattern data volume, and the length of the scan chains used for testing the imbedded repetitive structures is substantially reduced. The imbedded repetitive structures are tested by structuring and connecting the scan chain segments of the repeated structures in a way that permits identical test stimuli to be loaded into each copy of the repeated structure. A multiple input signature register or other such equivalent data compressing means provide the necessary data compression for reducing the volume of the test results that can be observed during scan by the tester to detect the presence of any fault that was observed.Type: GrantFiled: May 10, 2001Date of Patent: September 21, 2004Assignee: International Business Machines CorporationInventor: Carl F. Barnhart
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Publication number: 20040139377Abstract: A method an apparatus for testing logic circuits containing a set of scan chains, each set of scan chains comprising a multiplicity of scan chains. The apparatus comprising: a scan input; a scan output; an input shift register coupled between the scan input and the set of scan chains, each first stage of different scan chains of the set of scan chains coupled to a different stage of the input shift register; and an output shift register coupled between the scan output and the set of scan chains, each last stage of different scan chains coupled to a different stage of the output shift register.Type: ApplicationFiled: January 13, 2003Publication date: July 15, 2004Applicant: International Business Machines CorporationInventors: Carl F. Barnhart, Robert W. Bassett, L. Owen Farnsworth, Brion L. Keller, Bernd K.F. Koenemann
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Publication number: 20020170009Abstract: The test generation software takes advantage of the regularity of the structure without introducing significant changes to the test pattern generation software or to the manufacturing test tools. In this manner, the number of test patterns, the pattern data volume, and the length of the scan chains used for testing the imbedded repetitive structures is substantially reduced. The imbedded repetitive structures are tested by structuring and connecting the scan chain segments of the repeated structures in a way that permits identical test stimuli to be loaded into each copy of the repeated structure. A multiple input signature register or other such equivalent data compressing means provide the necessary data compression for reducing the volume of the test results that can be observed during scan by the tester to detect the presence of any fault that was observed.Type: ApplicationFiled: May 10, 2001Publication date: November 14, 2002Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: Carl F. Barnhart
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Publication number: 20020147559Abstract: METHOD FOR TESTING INTEGRATED LOGIC CIRCUITS A method of testing a circuit having multiple elements is disclosed. A plurality of faults representing the elements of the circuit for testing said circuit is created. The faults are grouped based on common attributes of the faults. A test pattern for each group of faults is created. Finally, the circuit is tested using test patterns for each group of faults.Type: ApplicationFiled: April 5, 2001Publication date: October 10, 2002Inventors: Carl F. Barnhart, Robert W. Bassett, Brion L. Keller, David E. Lackey, Mark R. Taylor, Donald L. Wheater
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Patent number: 4205303Abstract: Circuitry and method for adding, subtracting, multiplying and/or dividing a plurality of multi-bit, arbitrarily signed, changeable, coded digital input signals representing numerical values to convert said signals into a single analog output signal of predetermined amplitude having a fixed period but a duty cycle that is proportional to the algebraic sum or product or quotient of said input signals. This is accomplished using indirect digital-to-analog conversion.Type: GrantFiled: March 31, 1978Date of Patent: May 27, 1980Assignee: International Business Machines CorporationInventor: Carl F. Barnhart