Abstract: In one embodiment, a network device is disclosed. For example, in one embodiment of the present invention, the device comprises a processor and a core memory having a receive buffer and a transmit buffer. The device comprises a bus coupled to the processor and the core memory. The device comprises at least one co-processor coupled to the core memory via a direct link, wherein the at least one co-processor is capable of accessing at least one of: the receive buffer, or the transmit buffer, without assistance from the processor.

Abstract: In one embodiment, a device is disclosed. For example, in one embodiment of the present invention, the device comprises a memory core having a shared buffer, and an arbitration logic module for receiving a destination ready signal from a processing source of a plurality of processing sources. The device also comprises at least one pipeline stage for storing at least one piece of data read from the shared buffer, and at least one matching pipeline stage storing at least one valid signal associated with the at least one piece of data read from the shared buffer. The device also comprises a counter for storing a value, wherein the value represents a number of pieces of data read from the shared buffer, but have not been delivered to the processing source.