Abstract: A pattern for a wafer for a MOS-gated semiconductor device includes plural ribbons extending from a source contact region to another source contact region, each of the ribbons having a single source region between two channel regions, so as to increase the device's current-carrying capability per unit area relative to the prior art. The pattern increases the size of the active current-carrying area (the channel and neck regions of the device) relative to the area of the source contact areas. The source contact regions may be discrete or linear, and the ribbons may extend therefrom perpendicularly or at other angles.

Abstract: A MOS-gated semiconductor device may be manufactured by a process in which the neck region of the device is doped through a previously deposited polysilicon gate. In the method of the present invention, the dopant in the neck region of the device is not subjected to the same temperature history as the body dopant, thereby providing means to increase the ruggedness of the device and providing means by which the threshold voltage of the device may be controlled.

Abstract: A pattern for a wafer for a MOS-gated semiconductor device includes plural ribbons extending from a source contact region to another source contact region, each of the ribbons having a single source region between two channel regions, so as to increase the device's current-carrying capability per unit area relative to the prior art. The pattern increases the size of the active current-carrying area (the channel and neck regions of the device) relative to the area of the source contact areas. The source contact regions may be discrete or linear, and the ribbons may extend therefrom perpendicularly or at other angles.

Abstract: A VDMOS device includes a wafer of semiconductor material having first and second opposed major surfaces. A drain region of a first conductivity type extends along the one major surface. A plurality of body regions of a second conductivity type is in the body region at the one major surface. Each body region forms with the drain region a body/drain PN junction, the intersection of which with the first major surface is in a closed path, preferably a hexagon. A plurality of spaced source regions of the one conductivity type are in each of the body regions with each source region being positioned opposite the space between two source regions in the adjacent body region. Each source region forms with the body region a source/body PN junction. A portion of each of the source/body PN junctions is adjacent to but spaced from its respective drain/body PN junction to form a channel region therebetween. An insulated gate is over the first major surface and the channel regions.

Abstract: The present invention relates to a power MOS transistor having a current limiting circuit incorporated in the same substrate as the transistor. The power MOS transistor includes a drain region extending through the substrate between opposed first and second surfaces, a plurality of body regions in the substrate at the first surface, a separate source region in the substrate at the first surface within each body region and a channel extending across each body region between its junction with its respective source region and its junction with the drain region. A conductive gate is over and insulated from the first surface and extends over the channel regions. A first conductive electrode extends over and is insulated from the gate and contacts a first portion of the source regions. A second conductive electrode extends over and is insulated from the gate and contacts a second portion of the source regions. The second portion contains a smaller number of the source regions than the first portion.

Abstract: A fast switch-off circuit for a conductivity modulated field effect transistor (COMFET) avoids the flow of destructive latch-up currents. A reduced-amplitude switch-off current is applied to the gate electrode of the COMFET during the initial portion of switch-off. When the source-to-drain voltage (V.sub.DS) of the COMFET has become larger than the range of low V.sub.DS voltage in which latch-up can occur for an increased-amplitude switch-off current being applied to the gate electrode of the COMFET, that increased-amplitude switch-off current is applied to the gate electrode of the COMFET.

Abstract: An IGFET device includes a semiconductor wafer having a first conductivity type drain region contiguous with a wafer surface. A second conductivity type body region extends into the wafer from the wafer surface so as to form a body/drain PN junction having an intercept at the surface; the body region further including a body-contact portion of relatively high conductivity disposed at the surface. A first conductivity type source region extends into the wafer so as to form a source/body PN junction which has first and second intercepts at the surface. The first intercept is spaced from the body/drain intercept so as to define a channel region in the body region at the surface, and the second intercept is contiguous with the body contact portion. The second intercept is relatively narrowly spaced from the first intercept along most of the length of the first intercept and is relatively widely spaced from the first intercept at one or more predetermined portions.

Abstract: A VDMOS device comprises a semiconductor wafer having a major surface with a first conductivity type drain region thereat. An array of second conductivity type body regions, spaced from each other by distance D, is diffused into the drain region from the first surface. The body regions each include a relatively high conductivity supplementary body region and a first conductivity type source region diffused therein from within the first surface boundary thereof. The spacing between each source region and the drain region defines a channel region at the first surface. A source electrode contacts the source and body regions and an insulated gate electrode overlies each channel region. A gate bond pad, in direct contact with the gate electrode, overlies a second conductivity type gate shield region and is insulated therefrom. The gate shield region is contiguous with the drain region and is spaced from the neighboring channel regions by distance D.

Abstract: A vertical MOSFET device includes a major surface having an active, gate-controlled portion adjacent to an inactive portion. A gate-controlled perimeter channel is disposed at the boundary between the active and inactive portions.

Abstract: A differential amplifier stage is disclosed which utilizes opposed pairs of complementary transistors. The emitter electrodes of the complementary transistors of each pair are connected via matched resistors. A second matched pair of resistors are connected between the emitter electrodes of the input transistor of each complementary transistor pair. The interconnection of the second match pairs of resistors is connected to the base electrodes of the other transistors of each complementary transistor pair by a diode. A constant bias current is applied to the diode-transistor interconnection to provide current to the second pair of resistors to develop like potentials. These potentials establish floating bias potentials across the matched resistors in the emitter circuits of the complementary transistor pairs and thereby establish bias current in the transistors.

Abstract: A transistor having increased reverse second breakdown capabilities includes a collector formed with a high resistivity region including a channel portion adjacent the central portion of the emitter and with a lower resistivity region forming an interface around said channel portion. The second region is arranged to include a portion located laterally inwardly of the outer edges of the emitter so that a preferential current path is provided that defocuses the minority carriers injected by the emitter during the time the transistor is being switched off.

Abstract: A vertical MOSFET device having source, body and drain regions, includes an anode region in series with the drain region. The source, body and drain regions have a first forward current gain and the anode, drain and body regions have a second forward current gain, such that the sum of the current gains is less than unity. The anode region provides minority carrier injection into the drain region, enhancing device performance in power applications.

Abstract: A Schottky barrier contact is formed by depositing the conductor portion of the Schottky barrier contact on a surface of a semiconductor from which a conductivity determining dopant has been leached to create a surface region of reduced dopant concentration. This process is compatible with the formation of an ohmic contact to an increased conductivity portion of the semiconductor material, an unleached portion of the semiconductor material or to a leached portion of the semiconductor material.

Abstract: A temperature-independent reference voltage is developed as the difference between the offset potentials across first and second diode means, the second nested within the first to conduct the same forward bias current.

Abstract: A balanced-to-single-ended signal converter includes a pair of transistors of the same conductivity type responsive to balanced signals applied to their respective base electrodes to provide a single-ended signal at the interconnection of their serially connected collector-to-emitter paths.

Abstract: A circuit for quickly discharging a timing capacitor which is connected between the collector of a first transistor and the base of a second transistor, and which is charged via a current source connected to the collector of the first transistor. The circuit includes a third transistor whose conduction path is connected across the capacitor and whose control electrode is connected to the emitter of the first transistor. A turn-on current supplied to the base of the first transistor causes the timing capacitor to be discharged by a current whose amplitude is approximately equal to the turn-on current multiplied by the product of the forward current gains of the first and third transistors.

Abstract: A multivibrator in which a timing capacitor is connected between the collector of a first transistor and the base of a second transistor and in which a current source connected to the collector of the first transistor provides the charging current for the timing capacitor. The conduction path of a third transistor is connected between the collector and base of the first transistor and its control electrode is connected to a control voltage point for controlling the charging period of the capacitor and for ensuring oscillation when the multivibrator is connected as an astable multivibrator.