Abstract: A data transmission system, in which data streams shall be transmitted with great speed between a sending clock domain and a receiving clock domain, which operate with mutually different clock speeds, includes two system part circuits. One of these system part circuits is designed to receive from the first clock domain a data stream with the clock speed of the first clock domain and, controlled by this clock speed, serial/parallel convert the data stream to parallel data streams, each with a clock speed that is a certain fraction of the clock speed of the first clock domain. The other system part circuit is designed to receive the parallel data streams and, controlled by the clock speed of the other clock domain, parallel/serial convert them to an output data stream, which with the clock speed of the second clock domain is sent to the second clock domain.

Abstract: A limiting amplifier has between an amplifier input and an amplifier output at least one amplifier stage as well as load components. The amplifier has an output signal limiting device for limiting the maximum amplitude of the output signal and the amplification and includes a current drain device connected to the amplifier stage output and drawing current through the load components. More particularly, the amplifier stage can be a differential amplifier stage with a differential input and a differential output, two current drain devices being connected to each one of the terminals of the differential output.