Abstract: A microelectronic device, a semiconductor package including the device, an IC device assembly including the package, and a method of making the device. The device includes a substrate; a first structure on the substrate, the first structure corresponding to a front end of line (FEOL) stack of the device and including a plurality of first transistors therein; and a second structure on the substrate, the second structure corresponding to a back end of line (BEOL) stack of the device, and including a plurality of second transistors therein, the plurality of second transistors including a transition metal dichalcogenide (TMD) material. The second transistors are part of a voltage regulation architecture to regulate voltage supply to the die.

Abstract: In one embodiment, a transistor device includes a metal layer, a first dielectric layer comprising Hafnium and Oxygen on the metal layer, a channel layer comprising Tungsten and Selenium above the dielectric layer, a second dielectric layer comprising Hafnium and Oxygen on the channel layer, a source region comprising metal on a first end of the channel layer, a drain region comprising metal on a second end of the channel layer opposite the first end, and a metal contact on the second dielectric layer between the source regions and the drain region. In some embodiments, the transistor device may be included in a complementary metal-oxide semiconductor (CMOS) logic circuit in the back-end of an integrated circuit device, such as a processor or system-on-chip (SoC).

Abstract: Described herein are integrated circuit devices with conductive regions formed from MX or MAX materials. MAX materials are layered, hexagonal carbides and nitrides that include an early transition metal (M) and an A group element (A). MX materials remove the A group element. MAX and MX materials are highly conductive, and their two-dimensional layer structure allows very thin layers to be formed. MAX or MX materials can be used to form several conductive elements of IC circuits, including contacts, interconnects, or liners or barrier regions for contacts or interconnects.

Abstract: Disclosed herein are transistors including two-dimensional materials, as well as related methods and devices. In some embodiments, a transistor may include a first two-dimensional channel material and a second two-dimensional source/drain (S/D) material in a source/drain (S/D), and the first two-dimensional material and the second two-dimensional material may have different compositions or thicknesses. In some embodiments, a transistor may include a first two-dimensional material in a channel and a second two-dimensional material in a source/drain (S/D), wherein the first two-dimensional material is a single-crystal material, and the second two-dimensional material is a single-crystal material.

Abstract: Disclosed herein are transistors including two-dimensional materials, as well as related methods and devices. In some embodiments, a transistor may include a first two-dimensional channel material and a second two-dimensional source/drain (S/D) material in a source/drain (S/D), and the first two-dimensional material and the second two-dimensional material may have different compositions or thicknesses. In some embodiments, a transistor may include a first two-dimensional material in a channel and a second two-dimensional material in a source/drain (S/D), wherein the first two-dimensional material is a single-crystal material, and the second two-dimensional material is a single-crystal material.