Abstract: A method of characterizing a circuit comprises the steps of measuring a first delay associated with the circuit when the circuit is substantially unloaded; measuring a second delay associated with the circuit when the circuit is loaded by a predetermined impedance; determining a difference between the second delay and the first delay, the delay difference corresponding to a switching impedance associated with the circuit; and determining a characterization parameter of the circuit, the characterization parameter being a function of at least the switching impedance associated with the circuit. The methodologies of the present invention are directed primarily to individually evaluating pullup and pulldown delays with substantial precision (e.g., sub-picosecond) for a representative set of circuits in the presence of an arbitrary switching history.

Abstract: A method of characterizing a circuit comprises the steps of measuring a first delay associated with the circuit when the circuit is substantially unloaded; measuring a second delay associated with the circuit when the circuit is loaded by a predetermined impedance; determining a difference between the second delay and the first delay, the delay difference corresponding to a switching impedance associated with the circuit; and determining a characterization parameter of the circuit, the characterization parameter being a function of at least the switching impedance associated with the circuit. The methodologies of the present invention are directed primarily to individually evaluating pullup and pulldown delays with substantial precision (e.g., sub-picosecond) for a representative set of circuits in the presence of an arbitrary switching history.

Abstract: A method and system for testing an integrated circuit. A test substrate is provided which is manufactured by the same particular production technology for which the integrated circuit is designed. A pattern generator for generating test data and a result checker for comparing output data are embedded on the test substrate. Isolated portions of circuitry of the integrated circuit are selectively embedded onto the test substrate. Test data from the pattern generator is applied to the isolated portions of circuitry under a first operating condition. The data output from the isolated portions of circuitry is selectively recorded into the result checker. The isolated portions of circuitry are then subjected to testing by applying test data from the pattern generator to the isolated portions of circuitry under a second operating condition.

Abstract: A battery grid plate composition comprising by percent weight:______________________________________ Calcium .035-.085 Tin 1.2-1.55 Silver .002-.

Abstract: A boat construction incorporating unique structural features for improved performance at a variety of speeds and water depths. The hull of the boat incorporates a deep-V forward section and a rear tunnel section extending longitudinally rearward from a midpoint of the boat. A vertically adjustable outboard is positioned at the forward end of the tunnel section of the hull. The outboard engine may be vertically adjusted to accommodate different water depths and operational requirements. The engine is positioned within a console above the midpoint for convenient maintenance access and insulation against engine noise. Steering may be accomplished by rotating the engine itself or separately through rudders mounted to the hull. The center mounting of the engine in conjunction with the tunnel section of the hull reduces planing upon acceleration, improves center of gravity and reduces the risk to swimmers and water skiers from a rear mounted propeller.

Abstract: A laminated windshield in which thin solar cells are sandwiched between the glass layer. The solar cell is electrically connected to a vehicle battery to provide recharging current to the battery from the electrical current generated by the solar cells. The solar cells may be formed of dendrite solar cells arranged in flexible strings. These solar cell strings may be positioned in the windshield proximate to an edge of the windshield and superimposed over windshield tinting or darkened border areas of the windshield.

Abstract: The present invention is a fully integrated digital filter which interacts with a phase comparator to provide a phase lock loop and data retiming function. The digital filter includes a prescaler, a six bit reversible counter, and a four bit reversible counter. The phase comparator is a D-type edge-triggered flip-flop in which an input data signal clocks the flip-flop and samples a clock signal to determine whether the clock signal leads or lags the input data signal. The clock signal is repeatedly sampled and the digital filter counts the number of leading and lagging signals. The digital filter counts the leading and lagging signals in groups so that the counting rate of the digital filter does not have to be as high as the input data rate. The prescaler groups the bits and the six bit counter determines the number of samples that indicate a clock lead or lag.

Abstract: A GaAs differential current switch (DCS) logic family is disclosed. Two cross-coupled, push-pull output buffer stages are coupled to the DCS logic circuit to increase the gain and to improve noise margins. The circuit is compatible with other GaAs logic families such as super buffer logic (SBL) or source follower logic (SFFL).

Abstract: A paper towel holder apparatus has a base plate mountable on a support surface and a means for rotatably holding a roll of paper towels for rotation of the roll of towels on its axis. An arcuate frame has a cylindrical brake bar mounted on one side thereof and fasteners rotatably fastening the arcuate frame to the base plate below the center axis and parallel to the center axis of a roll of paper towels held in the paper towel holder. The arcuate frame brake extends parallel to the axis of the roll of paper towels and is supported on the roll of towels along the top of the roll so that the arcuate frame extends at least 90.degree. around a roll of paper towels to prevent the towels from being blown by air movement and to provide a brake for tearing the paper towels.

Abstract: A storage battery, such as for automotive applications, which employs a novel one piece low profile cover attachable to a conventional battery container. The cover includes two pairs of battery terminals for receiving pressure clamp battery cables ends or battery cable ends designed for attachment to side mount terminals. The cover also includes a movable handle which is an integral part of the cover and which is completely stowable in a recess in the cover.

Abstract: Digital logic driving stage circuitry is provided connected between ground and a single voltage with an enhancement mode type field effect transistor and a depletion mode type field effect transistor connected source to drain in series between the single voltage and ground. The gate of the enhancement mode type field effect transistor is the input of the logic signal and the gate of the depletion mode type field effect transistor is connected to ground, with the output at the connection between the transistors. A family of digital logic circuits is provided with circuit units made up of an enhancement mode logic input, depletion mode load circuitry stage and an enhancement mode input grounded source follower load driving stage.

Abstract: In an analog-to-digital converter implemented in logic operating on the multiple lobes of a threshold curve, such as Josephson SQUIDs, two sampling registers are provided with sufficient offset to guarantee stability at sampling in one or the other regardless of other factors. Knowledge of bit value of the next lower bit order position permits determination of which sampling is valid. Encoder logic selects the valid sampling register retroactively.Each sampling register bit order position has two sampling SQUIDs and latching self-gated ANDs. Bias values are provided at higher orders to increment the phase offset so as to ensure low-to-high order readout.The lowest two bit orders may be implemented in simplified logic, effectively giving two bit order positions for logic and SQUIDs equal to that of one higher order bit position.

Abstract: A transmission line having substantially reduced far-end forward wave crosstalk is characterized by a single layer of dielectric material having a thickness chosen to provide a forward wave coupling constant K.sub.F substantially equal to zero. The dielectric layer is located on a ground plane, and has a plurality of signal carrying conductors embedded in it. The thickness H of the dielectric underlayer below the signal carrying conductors is chosen to provide a transmission line having the selected values of impedance, etc. and substantially reduced forward wave crosstalk. The thickness t of the dielectric overlayer above the signal carrying conductors is chosen (for the selected value of thickness H of the dielectric underlayer) at the finite value critical thickness at which forward wave mutual capacitance and forward wave mutual inductance cancel to a null. The ground plane and the signal carrying conductors can be superconductors.