Abstract: Disclosed embodiments relate to atomic memory operations. In one example, an apparatus includes multiple processor cores, a cache hierarchy, a local execution unit, and a remote execution unit, and an adaptive remote atomic operation unit. The cache hierarchy includes a local cache at a first level and a shared cache at a second level. The local execution unit is to perform an atomic operation at the first level if the local cache is a storing a cache line including data for the atomic operation. The remote execution unit is to perform the atomic operation at the second level. The adaptive remote atomic operation unit is to determine whether to perform the first atomic operation at the first level or at the second level and whether to copy the cache line from the shared cache to the local cache.

Abstract: Embodiment of this disclosure provides a mechanism to use a portion of an inactive processing element's private cache as an extended last-level cache storage space to adaptively adjust the size of shared cache. In one embodiment, a processing device is provided. The processing device comprising a cache controller is to identify a cache line to evict from a shared cache. An inactive processing core is selected by the cache controller from a plurality of processing cores associated with the shared cache. Then, a private cache of the inactive processing core is notified of an identifier of a cache line associated with the shared cache. Thereupon, the cache line is evicted from the shared cache to install in the private cache.

Abstract: Embodiment of this disclosure provides a mechanism to use a portion of an inactive processing element's private cache as an extended last-level cache storage space to adaptively adjust the size of shared cache. In one embodiment, a processing device is provided. The processing device comprising a cache controller is to identify a cache line to evict from a shared cache. An inactive processing core is selected by the cache controller from a plurality of processing cores associated with the shared cache. Then, a private cache of the inactive processing core is notified of an identifier of a cache line associated with the shared cache. Thereupon, the cache line is evicted from the shared cache to install in the private cache.

Abstract: A method of assembling executable instructions includes mapping a first file scope symbol table for a first source code file being assembled, the first file scope symbol table including a reference for each symbol declaration within each corresponding section of code, determining nested sections of code included in the first source code file, mapping a nested scope symbol table for each determined nested section of code, with each nested scope symbol table including a reference for each symbol declaration within each corresponding section of code and assembling a portion of an executable instruction that corresponds to a symbol reference included in a coded instruction, the portion of the executable instruction based on a symbol mapped by one of the symbol tables.

Abstract: A first simulation environment for use in multiple simulation environments includes a first simulator application. The first simulator application includes a first simulator and a first graphical user interface (GUI). The first simulator environment also includes a first simulator plug-in that is configured to interface the first simulator application with a second simulation environment.

Abstract: A method of assembling executable instructions includes mapping a first file scope symbol table for a first source code file being assembled, the first file scope symbol table including a reference for each symbol declaration within each corresponding section of code, determining nested sections of code included in the first source code file, mapping a nested scope symbol table for each determined nested section of code, with each nested scope symbol table including a reference for each symbol declaration within each corresponding section of code and assembling a portion of an executable instruction that corresponds to a symbol reference included in a coded instruction, the portion of the executable instruction based on a symbol mapped by one of the symbol tables.