Abstract: Cooperative patterns are formed in stencils and/or substrates that facilitate the monitoring and control of the circuit assembly process. A pattern of successively-larger etch blocks receives a corresponding pattern of same-size solder blocks; solder reflow problems are indicated when either too many or too few etch blocks are completely covered by solder after reflow. A pattern of same-size etch blocks receives a corresponding pattern of successively-larger solder blocks; problems with solder stencil clogging are indicated when smaller ones of the etch blocks do not receive solder paste during stenciling. Finally, component beacon openings or translucent areas are made in the electronics assembly at component locations. After component placement, the board is appropriately lit, and any uncovered openings indicate missing or grossly misaligned components.

Abstract: Etch features are included on a printed circuit (PC) board to be used in monitoring and controlling assembly processes such as soldering. A vernier pattern of etch blocks receives corresponding solder blocks during solder paste screening; misalignment of the solder stencil to the PC board is indicated by an easily-seen interference pattern of spaces created by the superimposed etch and solder blocks. The degree of misalignment can be determined by measuring the distance between the center of the interference pattern and a reference etch block. Also, a scale pattern of etch receives a bar of solder paste; misalignment in the direction orthogonal to the long axis of the scale is indicated by the location of the intersection of the long axis and the solder bar.