Abstract: A multicore processing environment (MCPE) is disclosed. In embodiments, the MCPE includes multiple processing cores hosting multiple user applications configured for simultaneous execution. The cores and user applications share system resources including main memory and input/output (I/O) domains, each I/O domain including multiple I/O devices capable of requesting inbound access to main memory through an I/O memory management unit (IOMMU). For example, the IOMMU cache associates unique cache tags to each I/O device based on device identifiers or settings determined by the system registers, caching the configuration data for each I/O device under the appropriate cache tag. When each I/O device requests main memory access, the IOMMU cache refers to the appropriate configuration data under the corresponding unique cache tag. This prevents contention in the IOMMU cache caused by one device evicting the cache entry of another, minimizing interference channels by reducing the need for main memory access.

Abstract: A redundant processing system with profile-based monitoring is disclosed. In embodiments, the redundant system includes two or more redundant lanes, each lane having equivalent processing components. In a testing state, template processors and hardware monitoring sensors are connected to a selected trusted lane and input vectors submitted thereto; the hardware sensors characterize the response of the selected lane and the resulting testing data compiled into system templates. In an operational environment, the template processors send challenges based on the input vectors to each of the redundant lanes in real time, collecting response data from each lane via identical sets of monitoring sensors. The template processors correlate the response data with the corresponding system templates, identifying anomalous lanes and system anomalies based on discorrelations between the response data and the system templates.

Abstract: A hardware malware profiling and detection system is disclosed. In embodiments, the system includes a primary (e.g., trusted) system including template processors and hardware sensors. The template processors submit input vectors to the primary system and characterize the system response via power trace data collected by the hardware sensors. Based on the input vectors and power trace data, the template processors generate system templates and derive system challenges therefrom. The template processors submit the system challenges to a remote system under test and characterize the remote system response in real time via identical remote hardware sensors. The template processors correlate the real-time remote system response data with the system templates corresponding to the issued challenges to detect system anomalies or malware within the remote system or its components.

Abstract: A redundant processing system with profile-based monitoring is disclosed. In embodiments, the redundant system includes two or more redundant lanes, each lane having equivalent processing components. In a testing state, template processors and hardware monitoring sensors are connected to a selected trusted lane and input vectors submitted thereto; the hardware sensors characterize the response of the selected lane and the resulting testing data compiled into system templates. In an operational environment, the template processors send challenges based on the input vectors to each of the redundant lanes in real time, collecting response data from each lane via identical sets of monitoring sensors. The template processors correlate the response data with the corresponding system templates, identifying anomalous lanes and system anomalies based on discorrelations between the response data and the system templates.

Abstract: A hardware malware profiling and detection system is disclosed. In embodiments, the system includes a primary (e.g., trusted) system including template processors and hardware sensors. The template processors submit input vectors to the primary system and characterize the system response via power trace data collected by the hardware sensors. Based on the input vectors and power trace data, the template processors generate system templates and derive system challenges therefrom. The template processors submit the system challenges to a remote system under test and characterize the remote system response in real time via identical remote hardware sensors. The template processors correlate the real-time remote system response data with the system templates corresponding to the issued challenges to detect system anomalies or malware within the remote system or its components.

Abstract: A multi-core processing environment (MCPE) capable of quantifying shared system resource (SSR) access includes several processing cores, each core having several applications running thereon and accessing SSRs via virtual machines (VM). Each core includes core-specific shared memory and a guest operating system (GOS) for writing timestamped VM data entries to a core-specific data queue, each entry identifying an activated VM and its activation time. Hypervisor-accessible memory stores performance monitor registers (PMR) for monitoring specific MCPE features as well as PMR data queues for each core, the PMR data including timestamped values of the monitored features. The hypervisor writes the VM/PMR data to the corresponding queues and frequently samples PMR data. A correlation module correlates the queued VM/PMR data to determine execution times of each activated VM and (for each execution time) counts of PMR changes, each PMR change corresponding to an SSR access by a core of the MCPE.

Abstract: A multicore processing environment (MCPE) implements a shared resource access rate (SRAR) safety net to limit the access of user applications to shared system resources (SSR). For each user application, a baseline shared resource access time (SRAT) and baseline SSR access rate (while no other competing applications interfere) may be determined. A utilization for each accessed SSR, including worst case execution time and contention SRAT for competing applications, may be determined. For the user application and competing applications, an access time delta for each accessed SSR and total delta may be determined. Based on the total delta and an access count for each SSR, a multicore derating for the user application may be determined and the time requirement adjusted or allocated to include the multicore derating and baseline SRAT. Accordingly, the core rate limiters may limit data access to each SSR by the user application to a corresponding expected value.

Abstract: Systems and methods for predicting and managing computation derations that may occur in multi-core processors are disclosed. The method may include: determining effects of multi-core contentions on a particular core of a multi-core processor; determining effects of single-core contentions on a particular hosted function hosted on the multi-core processor; determining an adjustment time to a baseline activation time for the particular hosted function, wherein the adjustment time plus the baseline activation time overcome the effects of multi-core contentions and single-core contentions at a predetermined probability goal; and adjusting a computation time requirement of the particular hosted function to include the adjustment time and the baseline activation time.