Abstract: A computer network system repetitively distributes messages including uniquely identified blocks of real time data containing a current data image over a broadcast communications network to all real time stations for storage of each repetition of each entire block of data directly in station memory at a unique address space assigned to that uniquely identified block of data. The real time stations receive the blocks of data and alternatively receive other messages from the real time stations. The other messages have a recognized standard protocol, such as the TCP/IP or UDP/IP protocol of the Internet Protocol Suite.

Abstract: The operating system clocks in each station on a counter rotating ring network of a distributed processing system are synchronized by latching the count in a free running counter in the network interface of each station at the instant a clock message transmitted by a timekeeper station is received. The timekeeper station then calculates from its operating system time-of-day clock and its free running counter, its time of reception of the clock message, and broadcasts this timekeeper time of reception to the other stations. Each other station calculates its own time of reception from its operating system time of day, and the count in its free running counter, and uses the difference between its time of reception and the timekeeper time of reception to correct its operating system time-of-day clock. Repeater and media propagation delays determined from the dynamic topography of the network are taken into account in calculating the correction factor.

Abstract: Real time periodic messages generated by a plurality of stations on a data communication network and having data periods ranging from a shortest to a longest, where the longest data period is an integer multiple of all the others, are assigned by a server station to transmit time slots, equal in duration to the shortest data period, on a global basis to minimize the number of messages transmitted by all stations during each transmit time slot.

Abstract: A data communications arrangement for a distributed processor control system having a number of stations which can send and receive control data, includes a communications processor at each station effective for controlling the flow of control data over a serial communications bus. The communications processor is coupled to a dual ported memory device along with a functional processor which is effective for carrying out the actual operations of the process. The communications control processor is further effective for assembling frames of control data according to a predetermined arrangement which gives a timing preference to a first category of data over a second category of data. The assembled frame of control data will then include all of the first category of data and, with time remaining from a timing goal, will include a portion of the second category of data.

Abstract: A communications arrangement for a distributed process control system operable to control an industrial process where different types of data must be communicated between a number of control drops or stations in varying timing priorities includes a first communication channel on which at least two of the control drops are connected. A second communication channel, independent of the first communication channel, accommodates the communication of a type of data that is not as critical in terms of timing as that which is communicated over the first communication channel. All of the control drops are connected to the second communication channel. A control processor, located at each of the control drops, determines the distribution of the types of data between the two communication channels according to a predetermined timing priority.

Abstract: A multiprocessor computer control system for a process includes at least two central processors and respectively associated input/output systems. Control system faults are detected and a bootstrap microprocessor is triggered into its fault detector and recovery mode. The output control signals are placed on and central processors are stopped and restarted and then it is determined which if any of them is to be inoperative. A reconfigured control system is defined with the inoperative unit(s) excluded. The microprocessor switches the input/output systems as necessary to structure the control system in reconfigured form so that process control can resume without disturbance.