Abstract: A reverberation processor and method for generating reverberation in a digital audio processing system. The reverberation processor uses register files programmed with tap page and tap offset addresses to gather the audio data for the reverberation taps. The address of each block transferred is determined by the tap number, which selects an offset register to provide a lower portion of the address, and the page number which selects a page register to provide the upper portion of the address. Control logic provides for enabling of the address and initiation of transfers to and from memory on a bus. Dual port register files are used to receive that data for a digital signal processor (DSP). The DSP computes a reverberation result and fills another dual port register file. The register files signal the control logic to initiate transfers when the input data drops below a threshold or the output data exceeds a threshold.

Abstract: A system is delineated comprising, in combination, an integrated circuit having N internal masters coupled to a buried, internal bus, and register circuitry coupled to the buried, internal bus and having an output providing status data for each of the N internal masters. The output from the register circuitry is directly coupled to a processor for permitting the processor to monitor request and grant status for each internal master, thereby allowing the processor to keep track of which, if any, of the internal masters attempt to "hog" the internal, buried bus. Additionally, the processor can set enabling registers located in the register circuitry to one value for permitting properly operating internal masters to have access to the internal, buried bus, and to another value to disable one or more "hogging" internal masters from accessing the internal, buried bus. The system further includes N external devices coupled, on a one-to-one basis, to the N internal masters.