Abstract: A system for enabling input/out virtualization for a device is disclosed. In one embodiment the system includes a plurality of host CPUs; a multi-root switch connected to each of the plurality of host CPUs via respective buses; and an inline PCI virtualizing device connected to the multi-root switch via a front-side bus and the device via a back-side bus, the inline PCI virtualizing device including a plurality sets of registers, each of the plurality sets of registers accessible by a corresponding host CPU of the plurality of host CPUs and implementing functionalities of the device.

Abstract: A system for enabling input/out virtualization for a device is disclosed. In one embodiment, the system includes a plurality of host CPUs; a multi-root switch connected to each of the plurality of host CPUs via respective buses; and an inline PCI virtualizing device connected to the multi-root switch via a front-side bus and the device via a back-side bus, the inline PCI virtualizing device including a plurality sets of registers, each of the plurality sets of registers accessible by a corresponding host CPU of the plurality of host CPUs and implementing functionalities of the device.

Abstract: A system for enabling input/out virtualization for a device is disclosed. In one embodiment, the system includes a plurality of host CPUs; a multi-root switch connected to each of the plurality of host CPUs via respective buses; and an inline PCI virtualizing device connected to the multi-root switch via a front-side bus and the device via a back-side bus, the inline PCI virtualizing device including a plurality sets of registers, each of the plurality sets of registers accessible by a corresponding host CPU of the plurality of host CPUs and implementing functionalities of the device.

Abstract: A system for enabling input/out virtualization for a device is disclosed. In one embodiment, the system includes a plurality of host CPUs; a multi-root switch connected to each of the plurality of host CPUs via respective buses; and an inline PCI virtualizing device connected to the multi-root switch via a front-side bus and the device via a back-side bus, the inline PCI virtualizing device including a plurality sets of registers, each of the plurality sets of registers accessible by a corresponding host CPU of the plurality of host CPUs and implementing functionalities of the device.

Abstract: A system for enabling input/out virtualization for a device is disclosed. In one embodiment the system includes a plurality of host CPUs; a multi-root switch connected to each of the plurality of host CPUs via respective buses; and an inline PCI virtualizing device connected to the multi-root switch via a front-side bus and the device via a back-side bus, the inline PCI virtualizing device including a plurality sets of registers, each of the plurality sets of registers accessible by a corresponding host CPU of the plurality of host CPUs and implementing functionalities of the device.

Abstract: A system for enabling input/out virtualization for a device is disclosed. In one embodiment, the system includes a plurality of host CPUs; a multi-root switch connected to each of the plurality of host CPUs via respective buses; and an inline PCI virtualizing device connected to the multi-root switch via a front-side bus and the device via a back-side bus, the inline PCI virtualizing device including a plurality sets of registers, each of the plurality sets of registers accessible by a corresponding host CPU of the plurality of host CPUs and implementing functionalities of the device.

Abstract: A system and method are disclosed for detecting and preventing bridge loops in a relatively low cost bridge module designed for installation in a network hub. The bridge operates to monitor an intra-hub communication path of the network hub to detect bridge protocol data units transmitted by a switching fabric within the network hub. The bridge module stores a MAC source address of a bridge protocol data unit detected on the intra-hub communications path, and forwards the bridge protocol data unit through its external communication ports to respective network segments. The bridge module monitors its external communication ports for any data unit having a destination address matching a bridge multicast address. When a data unit having a destination address matching the bridge multicast address is detected, the bridge module compares the MAC source address of that data unit to the previously stored MAC source address from the bridge protocol data unit detected on the intra-hub communication path.

Abstract: A computer network switch includes a receiving module for receiving packets, a packet memory with a plurality of buffer cells with each of the buffer cells having a buffer descriptor. A descriptor free pool lists available buffer descriptors that can be used for new incoming packets. A plurality of transmit queues hold the buffer descriptors. Each of the transmit queues include an input queue, an expansion queue and an output queue. The switch also includes control logic for directing the removing of one of the available buffer descriptors from the free pool and directing one of the packets from the receiving module into one of the buff cells corresponding to the one available buffer descriptor. The control logic places the one buffer descriptor in the input queue of one of the transmit queues. The control logic also monitors a load status of the input and output queues.

Abstract: A main data memory is provided in a network device and includes a plurality of buffers for storing data packets. A plurality of descriptors, or pointers, point to the individual buffers. A status of the descriptors is stored in a descriptor reference memory. The status information includes whether the descriptors are in an active or free state, and an indication of copies of the descriptors in the transmit queues. A descriptor free pool includes a list of the descriptors in the free state.

Abstract: A main data memory is provided in a network device and includes a plurality of buffers for storing data packets. A plurality of descriptors, or pointers, point to the individual buffers. A status of the descriptors is stored in a descriptor reference memory. The status information includes whether the descriptors are in an active or free state, and an indication of copies of the descriptors in the transmit queues. A descriptor free pool includes a list of the descriptors in the free state.

Abstract: A LAN to ATM switch module includes a memory with an ATM port, a LAN port and a processor port. Each of port separately reading and writing information to/from the memory. An ATM interface is included for reading information from the ATM port and converting the information into an ATM format. The ATM interface also converts ATM format information to be delivered to the ATM port and written to the memory. A LAN interface reads information from the LAN port and converts the information into LAN format. The LAN interface also converts LAN information from a LAN packet channel bus to the LAN port, to be written to the memory. The switch module also includes a processor for reading information in the memory through the processor port. The processor determines the processing need for the information, the processor modifies the information in the memory according to the processing needed by writing to the memory through the processor port and controlling the ATM and LAN interfaces according to the processing needed.

Abstract: A multiport or multiported memory device is provided. A first user and at least a second user are provided. A multilevel memory arbitration system is implemented which establishes arbitration cycles wherein the high priority user is granted priority as to access either during each arbitration cycle or during a greater number of arbitration cycles. A source burst limiter is provided associated with the high priority user. The source burst limiter monitors access of the high priority user to the multiport memory and limits such access based on a comparison of access attributes to some access attribute threshold.