Abstract: Controlling accesses to target devices such as disk drives by modifying the duty cycle profile of those devices to improve device reliability is disclosed. The utilization of a target device is monitored, and if a device is being overused, that device is given a rest period by reserving it for a special initiator that does not send any commands to the device for a certain period of time. This reduced utilization has the effect of increasing the reliability of the target device. This period of time also adds a delay to the processing of commands for the target device being overutilized so that the device becomes less responsive. This performance penalty creates pressure on system administrators to reduce the number of commands sent to that target device and/or move data to proper devices (that can handle the high number of accesses).

Abstract: Monitoring in switch networks is disclosed. Ports in a switch may include monitoring circuitry and a monitoring tap which allows traffic data to be diverted for monitoring prior to any significant transformation of the traffic by the regular port logic. Furthermore, the monitoring circuitry can receive signaling and convert it for subsequent analysis by a protocol analyzer. The ports and paths in the switch network can be configured to create monitor paths to enable diverted traffic data to be passed through the network to locations where a protocol analyzer can be easily attached. With wide bandwidth ports, there is no disruption to the system. Because only a copy of the data is routed to the analyzer, there is no change to the original signal path and latency is identical with or without the analyzer.

Abstract: A device, integrated circuit and method for generating simulated errors are disclosed. In the disclosed device, integrated circuit and method, an original data value is read from a memory. The original data value is intercepted by the integrated circuit. The integrated circuit is operable to virtualize an error in the original data value to generate a modified data value. The integrated circuit is also operable to generate an interrupt according to the virtualization. This disclosure may be particularly useful for high-level memory validation.

Abstract: Snooping in SAS expander networks is disclosed. Ports in a SAS expander may include snoop circuitry and a snoop tap which allows snoop data to be diverted for snooping prior to any significant transformation of the traffic by the regular port logic. Furthermore, the snoop circuitry can receive OOB signaling and convert it to K characters for transmission through the SAS network and subsequent analysis by a protocol analyzer. The ports and cascades in the expander network can be configured to create snoop paths to enable snoop data to be passed through the network to locations where a protocol analyzer can be easily attached. With SAS snoop ports, there is no disruption to the system. Because only a copy of the data is routed to the analyzer, there is no change to the original signal path and latency is identical with or without the analyzer.

Abstract: A device, integrated circuit and method for generating simulated errors are disclosed. In the disclosed device, integrated circuit and method, an original data value is read from a memory. The original data value is intercepted by the integrated circuit. The integrated circuit is operable to virtualize an error in the original data value to generate a modified data value. The integrated circuit is also operable to generate an interrupt according to the virtualization. This disclosure may be particularly useful for high-level memory validation.

Abstract: Embodiments of the invention enable error simulation for system validation. Errors can be simulated by modifying data presented to the processor as well as generating interrupts consistent with the modified data in the ASIC hardware. Modify logic may be added to the ASIC so when the microprocessor attempts to read a specific address, the modify logic may mask one or more of the data bits returned by the requested address. Address, bit mask, and force value data may be stored in registers to determine which address may be modified, the bit location to be modified, and the value that bit location should be changed to. Selection logic may then determine whether data from the modify logic or the unmodified value from an attached device should be sent to the ASIC interface and on to the microprocessor. A timer may also be used to decouple the setup from the test.

Abstract: Embodiments of the invention enable error simulation for system validation. Errors can be simulated by modifying data presented to the processor as well as generating interrupts consistent with the modified data in the ASIC hardware. Modify logic may be added to the ASIC so when the microprocessor attempts to read a specific address, the modify logic may mask one or more of the data bits returned by the requested address. Address, bit mask, and force value data may be stored in registers to determine which address may be modified, the bit location to be modified, and the value that bit location should be changed to. Selection logic may then determine whether data from the modify logic or the unmodified value from an attached device should be sent to the ASIC interface and on to the microprocessor. A timer may also be used to decouple the setup from the test.

Abstract: This invention relates to error simulation for system validation. Errors can be simulated by modifying data presented to the processor as well as generating interrupts consistent with the modified data in the ASIC hardware. Modify logic may be added to the ASIC so when the microprocessor attempts to read a specific address, the modify logic may mask one or more of the data bits returned by the requested address. Address, bit mask, and force value data may be stored in registers to determine which address may be modified, the bit location to be modified, and the value that bit location should be changed to. Selection logic may then determine whether data from the modify logic or the unmodified value from an attached device should be sent to the ASIC interface and on to the microprocessor. A timer may also be used to decouple the setup from the test.

Abstract: Described herein is an improved mechanism for bridging between SAS and SATA drives based upon existing SAS expanders in a SAS domain. In particular, a bridge capable of translating between SAS and SATA protocols is embedded in or coupled to an expander. When a SAS initiator request is received at the expander, the expander can route the request, based on a routing table, either directly to a destination SAS device or to the bridge for necessary translation before it is transmitted to a destination SATA drive. The routing table includes corresponding relationships between all SAS addresses and Phys through which those SAS and SATA devices are attached to the expander. SATA devices can be virtualized in the expander through a few assigned addresses in the routing table in a SAS discovery process.

Abstract: Described herein is an improved mechanism for bridging between SAS and SATA drives based upon existing SAS expanders in a SAS domain. In particular, a bridge capable of translating between SAS and SATA protocols is embedded in or coupled to an expander. When a SAS initiator request is received at the expander, the expander can route the request, based on a routing table, either directly to a destination SAS device or to the bridge for necessary translation before it is transmitted to a destination SATA drive. The routing table includes corresponding relationships between all SAS addresses and Phys through which those SAS and SATA devices are attached to the expander. SATA devices can be virtualized in the expander through a few assigned addresses in the routing table in a SAS discovery process.

Abstract: The attaching of labels to an OPEN frame and applying label switched routing to SAS expanders is disclosed to eliminate the need for large routing tables in SAS networks. A label stack is inserted into the OPEN frame by the initiator, prior to the OPEN frame being transmitted. Each label contains the egress port for a SAS expander in the transmit path. Each SAS expander to be participating in the connection reads the labels to determine the egress port to connect to and through which data is to be sent. The SAS expander marks its label invalid or discards it and forwards the OPEN frame to the egress port where the next SAS expander will look for the first valid label. The process repeats until the OPEN frame reaches the edge device, at which time all labels are discarded and the OPEN frame is forwarded to the end device.

Abstract: A system for enabling SATA drives to be utilized in FC SANs is disclosed. To send SATA FISs to a SATA drive over a FC SAN, a host sends SCSI commands encapsulated in FC frames over a standard FC link to a Fiber Channel Attached SATA Tunneling (FAST) RAID controller, where the SCSI commands are de-encapsulated from the FC frames and translated to SATA FISs. The SATA FISs are thereafter encapsulated into FC frames. The IOC that performs these functions is referred to as a FAST IOC. The SATA-encapsulated FC frames are sent to multiple disk drive enclosures over another standard FC link. The FC frames are de-encapsulated by FAST switches in disk drive enclosures to retrieve the SATA FISs, and the SATA FISs are sent to the SATA drives over a SATA connection.

Abstract: Embodiments of the present invention are directed to controlling device access fairness in frame-based switches by automatically and continuously counting the number of actively communicating devices connected to each port and the type of devices connected to each port, and adjusting fairness accordingly. During a sampling window, the number of active devices and the type of devices connected to each port is determined. At the start of each fairness window, a weighted number of slots are assigned to each port based on the number of active devices connected to each port and the type of devices connected to that port. Within a single fairness window, each port is able to provide device accesses to the frame-based switch in accordance with the number of slots assigned to that port.

Abstract: A system for enabling SATA drives to be utilized in FC SANs is disclosed. To send data to a SATA drive over a FC SAN, a host sends SCSI commands encapsulated in FC frames over a standard FC link to a Fibre Channel Attached SATA Tunneling (FAST) RAID controller, where the SCSI commands are de-encapsulated from the FC frames and translated to SATA FISs. The SATA FISs are thereafter encapsulated into FC frames. The IOC that performs these functions is referred to as a FAST IOC. The SATA-encapsulated FC frames are sent to multiple disk drive enclosures over another standard FC link. The FC frames are de-encapsulated by FAST switches in disk drive enclosures to retrieve the SATA FISs, and the SATA FISs are sent to the SATA drives over a SATA connection.

Abstract: The discovery and configuration of devices of interest connected to the Ethernet by an Ethernet port is disclosed. To perform discovery, Client software in a management interface transmits packets including the address of the management interface and a port identifier to a known broadcast address, requesting the MAC address for all devices of interest. Server software in the devices of interest parse the broadcast packets and broadcast a packet containing a MAC address that uniquely identifies the devices of interest back to the Client. Once the MAC addresses are returned to the Client, the Client can then broadcast protocol packets requesting the configuration of a specific device of interest such as a new IP address. Once a device of interest is configured with at least an IP address, the device of interest can communicate using TCP/IP, and it can thereafter be managed using higher level tools and firmware.

Abstract: Embodiments of the invention enable error simulation for system validation. Errors can be simulated by modifying data presented to the processor as well as generating interrupts consistent with the modified data in the ASIC hardware. Modify logic may be added to the ASIC so when the microprocessor attempts to read a specific address, the modify logic may mask one or more of the data bits returned by the requested address. Address, bit mask, and force value data may be stored in registers to determine which address may be modified, the bit location to be modified, and the value that bit location should be changed to. Selection logic may then determine whether data from the modify logic or the unmodified value from an attached device should be sent to the ASIC interface and on to the microprocessor. A timer may also be used to decouple the setup from the test.

Abstract: A method is disclosed for maintaining a table of recent accesses for each port for use in predicting whether a request for data from a source device is likely to be sent to a high speed or low speed destination device. The table of recent accesses lists every source device attached to that port and the speed of the destination device with the most recent access to each source device. When an OPN primitive is received at the source port, the source device is identified and used with the table of recent accesses to predict whether the destination device is likely to be high speed or low speed, and ultimately whether to send data from the source device or reject the request.

Abstract: Snooping in SAS expander networks is disclosed. Ports in a SAS expander may include snoop circuitry and a snoop tap which allows snoop data to be diverted for snooping prior to any significant transformation of the traffic by the regular port logic. Furthermore, the snoop circuitry can receive OOB signaling and convert it to K characters for transmission through the SAS network and subsequent analysis by a protocol analyzer. The ports and cascades in the expander network can be configured to create snoop paths to enable snoop data to be passed through the network to locations where a protocol analyzer can be easily attached. With SAS snoop ports, there is no disruption to the system. Because only a copy of the data is routed to the analyzer, there is no change to the original signal path and latency is identical with or without the analyzer.

Abstract: The attaching of labels to an OPEN frame and applying label switched routing to SAS expanders is disclosed to eliminate the need for large routing tables in SAS networks. A label stack is inserted into the OPEN frame by the initiator, prior to the OPEN frame being transmitted. Each label contains the egress port for a SAS expander in the transmit path. Each SAS expander to be participating in the connection reads the labels to determine the egress port to connect to and through which data is to be sent. The SAS expander marks its label invalid or discards it and forwards the OPEN frame to the egress port where the next SAS expander will look for the first valid label. The process repeats until the OPEN frame reaches the edge device, at which time all labels are discarded and the OPEN frame is forwarded to the end device.