Patents by Inventor Carl Joseph Neufeld
Carl Joseph Neufeld has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230335464Abstract: A semiconductor device comprises a III-N device including an insulating substrate. The insulating substrate includes a first side and a second side. The device further includes a III-N material structure on a first side of the insulating substrate, and a gate electrode, a source electrode, and a drain electrode on a side of the III-N material structure opposite the substrate. A backmetal layer on the second side of the insulating substrate, and a via hole is formed through the III-N material structure and the insulating substrate. A metal formed in the via-hole is electrically connected to the drain electrode on the first side of the substrate and electrically connected to the backmetal layer on the second side of the substrate.Type: ApplicationFiled: September 17, 2021Publication date: October 19, 2023Inventors: Geetak Gupta, Umesh Mishra, Davide Bisi, David Michael Rhodes, Rakesh K. Lal, Carl Joseph Neufeld
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Patent number: 11322599Abstract: A transistor includes a III-N channel layer; a III-N barrier layer on the III-N channel layer; a source contact and a drain contact, the source and drain contacts electrically coupled to the III-N channel layer; an insulator layer on the III-N barrier layer; a gate insulator partially on the insulator layer and partially on the III-N channel layer, the gate insulator including an amorphous Al1-xSixO layer with 0.2<x<0.8; and a gate electrode over the gate insulator, the gate electrode being positioned between the source and drain contacts.Type: GrantFiled: January 13, 2017Date of Patent: May 3, 2022Assignee: Transphorm Technology, Inc.Inventors: Carl Joseph Neufeld, Mo Wu, Toshihide Kikkawa, Umesh Mishra, Xiang Liu, David Michael Rhodes, John Kirk Gritters, Rakesh K. Lal
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Patent number: 11121216Abstract: A III-N device includes a III-N layer structure including a III-N channel layer, a III-N barrier layer over the III-N channel layer, and a graded III-N layer over the III-N barrier layer having a first side adjacent to the III-N barrier layer and a second side opposite the first side; a first power electrode and a second power electrode; and a gate between the first and second power electrodes, the gate being over the III-N layer structure. A composition of the graded III-N layer is graded so the bandgap of the graded III-N layer adjacent to the first side is greater than the bandgap of the graded III-N layer adjacent to the second side. A region of the graded III-N layer is (i) between the gate and the second power electrode, and (ii) electrically connected to the first power electrode and electrically isolated from the second power electrode.Type: GrantFiled: March 9, 2020Date of Patent: September 14, 2021Assignee: Transphorm Technology, Inc.Inventors: Umesh Mishra, Rakesh K. Lal, Geetak Gupta, Carl Joseph Neufeld, David Rhodes
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Publication number: 20210043750Abstract: A transistor includes a III-N channel layer; a III-N barrier layer on the III-N channel layer; a source contact and a drain contact, the source and drain contacts electrically coupled to the III-N channel layer; an insulator layer on the III-N barrier layer; a gate insulator partially on the insulator layer and partially on the III-N channel layer, the gate insulator including an amorphous Al1-xSixO layer with 0.2<x<0.8; and a gate electrode over the gate insulator, the gate electrode being positioned between the source and drain contacts.Type: ApplicationFiled: January 13, 2017Publication date: February 11, 2021Inventors: Carl Joseph Neufeld, Mo Wu, Toshihide Kikkawa, Umesh Mishra, Xiang Liu, David Michael Rhodes, John Kirk Gritters, Rakesh K. Lal
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Publication number: 20200343375Abstract: A lateral III-N device has a vertical gate module with III-N material orientated in an N-polar or a group-III polar orientation. A III-N material structure has a III-N buffer layer, a III-N barrier layer, and a III-N channel layer. A compositional difference between the III-N barrier layer and the III-N channel layer causes a 2DEG channel to be induced in the III-N channel layer. A p-type III-N body layer is disposed over the III-N channel layer in a source side access region but not over a drain side access region. A n-type III-N capping layer over the p-type III-N body layer. A source electrode that contacts the n-type III-N capping layer is electrically connected to the p-type III-N body layer and is electrically isolated from the 2DEG channel when the gate electrode is biased relative to the source electrode at a voltage that is below a threshold voltage.Type: ApplicationFiled: July 8, 2020Publication date: October 29, 2020Inventors: Umesh Mishra, Davide Bisi, Geetak Gupta, Carl Joseph Neufeld, Brian L. Swenson, Rakesh K. Lal
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Patent number: 10756207Abstract: A lateral III-N device has a vertical gate module with III-N material orientated in an N-polar or a group-III polar orientation. A III-N material structure has a III-N buffer layer, a III-N barrier layer, and a III-N channel layer. A compositional difference between the III-N barrier layer and the III-N channel layer causes a 2DEG channel to be induced in the III-N channel layer. A p-type III-N body layer is disposed over the III-N channel layer in a source side access region but not over a drain side access region. A n-type III-N capping layer over the p-type III-N body layer. A source electrode that contacts the n-type III-N capping layer is electrically connected to the p-type III-N body layer and is electrically isolated from the 2DEG channel when the gate electrode is biased relative to the source electrode at a voltage that is below a threshold voltage.Type: GrantFiled: October 10, 2019Date of Patent: August 25, 2020Assignee: Transphorm Technology, Inc.Inventors: Umesh Mishra, Davide Bisi, Geetak Gupta, Carl Joseph Neufeld, Brian L. Swenson, Rakesh K. Lal
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Publication number: 20200212180Abstract: A III-N device includes a III-N layer structure including a III-N channel layer, a III-N barrier layer over the III-N channel layer, and a graded III-N layer over the III-N barrier layer having a first side adjacent to the III-N barrier layer and a second side opposite the first side; a first power electrode and a second power electrode; and a gate between the first and second power electrodes, the gate being over the III-N layer structure. A composition of the graded III-N layer is graded so the bandgap of the graded III-N layer adjacent to the first side is greater than the bandgap of the graded III-N layer adjacent to the second side. A region of the graded III-N layer is (i) between the gate and the second power electrode, and (ii) electrically connected to the first power electrode and electrically isolated from the second power electrode.Type: ApplicationFiled: March 9, 2020Publication date: July 2, 2020Inventors: Umesh Mishra, Rakesh K. Lal, Geetak Gupta, Carl Joseph Neufeld, David Rhodes
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Patent number: 10629681Abstract: A III-N device includes a III-N layer structure including a III-N channel layer, a III-N barrier layer over the III-N channel layer, and a graded III-N layer over the III-N barrier layer having a first side adjacent to the III-N barrier layer and a second side opposite the first side; a first power electrode and a second power electrode; and a gate between the first and second power electrodes, the gate being over the III-N layer structure. A composition of the graded III-N layer is graded so the bandgap of the graded III-N layer adjacent to the first side is greater than the bandgap of the graded III-N layer adjacent to the second side. A region of the graded III-N layer is (i) between the gate and the second power electrode, and (ii) electrically connected to the first power electrode and electrically isolated from the second power electrode.Type: GrantFiled: February 27, 2019Date of Patent: April 21, 2020Assignee: Transphorm Technology, Inc.Inventors: Umesh Mishra, Rakesh K. Lal, Geetak Gupta, Carl Joseph Neufeld, David Rhodes
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Publication number: 20200119179Abstract: A lateral III-N device has a vertical gate module with III-N material orientated in an N-polar or a group-III polar orientation. A III-N material structure has a III-N buffer layer, a III-N barrier layer, and a III-N channel layer. A compositional difference between the III-N barrier layer and the III-N channel layer causes a 2DEG channel to be induced in the III-N channel layer. A p-type III-N body layer is disposed over the III-N channel layer in a source side access region but not over a drain side access region. A n-type III-N capping layer over the p-type III-N body layer. A source electrode that contacts the n-type III-N capping layer is electrically connected to the p-type III-N body layer and is electrically isolated from the 2DEG channel when the gate electrode is biased relative to the source electrode at a voltage that is below a threshold voltage.Type: ApplicationFiled: October 10, 2019Publication date: April 16, 2020Inventors: Umesh Mishra, Davide Bisi, Geetak Gupta, Carl Joseph Neufeld, Brian L. Swenson, Rakesh K. Lal
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Publication number: 20190198615Abstract: A III-N device includes a III-N layer structure including a III-N channel layer, a III-N barrier layer over the III-N channel layer, and a graded III-N layer over the III-N barrier layer having a first side adjacent to the III-N barrier layer and a second side opposite the first side; a first power electrode and a second power electrode; and a gate between the first and second power electrodes, the gate being over the III-N layer structure. A composition of the graded III-N layer is graded so the bandgap of the graded III-N layer adjacent to the first side is greater than the bandgap of the graded III-N layer adjacent to the second side. A region of the graded III-N layer is (i) between the gate and the second power electrode, and (ii) electrically connected to the first power electrode and electrically isolated from the second power electrode.Type: ApplicationFiled: February 27, 2019Publication date: June 27, 2019Inventors: Umesh Mishra, Rakesh K. Lal, Geetak Gupta, Carl Joseph Neufeld, David Rhodes
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Patent number: 10224401Abstract: A III-N device includes a III-N layer structure including a III-N channel layer, a III-N barrier layer over the III-N channel layer, and a graded III-N layer over the III-N barrier layer having a first side adjacent to the III-N barrier layer and a second side opposite the first side; a first power electrode and a second power electrode; and a gate between the first and second power electrodes, the gate being over the III-N layer structure. A composition of the graded III-N layer is graded so the bandgap of the graded III-N layer adjacent to the first side is greater than the bandgap of the graded III-N layer adjacent to the second side. A region of the graded III-N layer is (i) between the gate and the second power electrode, and (ii) electrically connected to the first power electrode and electrically isolated from the second power electrode.Type: GrantFiled: May 31, 2017Date of Patent: March 5, 2019Assignee: Transphorm Inc.Inventors: Umesh Mishra, Rakesh K. Lal, Geetak Gupta, Carl Joseph Neufeld, David Rhodes
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Publication number: 20180158909Abstract: A III-N device includes a III-N layer structure including a III-N channel layer, a III-N barrier layer over the III-N channel layer, and a graded III-N layer over the III-N barrier layer having a first side adjacent to the III-N barrier layer and a second side opposite the first side; a first power electrode and a second power electrode; and a gate between the first and second power electrodes, the gate being over the III-N layer structure. A composition of the graded III-N layer is graded so the bandgap of the graded III-N layer adjacent to the first side is greater than the bandgap of the graded III-N layer adjacent to the second side. A region of the graded III-N layer is (i) between the gate and the second power electrode, and (ii) electrically connected to the first power electrode and electrically isolated from the second power electrode.Type: ApplicationFiled: May 31, 2017Publication date: June 7, 2018Inventors: Umesh Mishra, Rakesh K. Lal, Geetak Gupta, Carl Joseph Neufeld, David Rhodes
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Patent number: 9935190Abstract: A method of fabricating a III-N device includes forming a III-N channel layer on a substrate, a III-N barrier layer on the channel layer, an insulator layer on the barrier layer, and a trench in a first portion of the device. Forming the trench comprises removing the insulator layer and a part of the barrier layer in the first portion of the device, such that a remaining portion of the barrier layer in the first portion of the device has a thickness away from a top surface of the channel layer, the thickness being within a predetermined thickness range, annealing the III-N device in a gas ambient including oxygen at an elevated temperature to oxidize the remaining portion of the barrier layer in the first portion of the device, and removing the oxidized remaining portion of the barrier layer in the first portion of the device.Type: GrantFiled: March 9, 2016Date of Patent: April 3, 2018Assignee: Transphorm Inc.Inventors: Mo Wu, Rakesh K. Lal, Ilan Ben-Yaacov, Umesh Mishra, Carl Joseph Neufeld
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Patent number: 9490324Abstract: An N-polar III-N transistor includes a III-N buffer layer, a first III-N barrier layer, and a III-N channel layer, the III-N channel layer having a gate region and a plurality of access regions on opposite sides of the gate region. The compositional difference between the first III-N barrier layer and the III-N channel layer causes a conductive channel to be induced in the access regions of the III-N channel layer. The transistor also includes a source, a gate, a drain, and a second III-N barrier layer between the gate and the III-N channel layer. The second III-N barrier layer has an N-face proximal to the gate and a group-III face opposite the N-face, and has a larger bandgap than the III-N channel layer. The lattice constant of the first III-N barrier layer is within 0.5% of the lattice constant of the buffer layer.Type: GrantFiled: June 19, 2015Date of Patent: November 8, 2016Assignee: Transphorm Inc.Inventors: Umesh Mishra, Srabanti Chowdhury, Carl Joseph Neufeld
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Publication number: 20160190298Abstract: A method of fabricating a III-N device includes forming a III-N channel layer on a substrate, a III-N barrier layer on the channel layer, an insulator layer on the barrier layer, and a trench in a first portion of the device. Forming the trench comprises removing the insulator layer and a part of the barrier layer in the first portion of the device, such that a remaining portion of the barrier layer in the first portion of the device has a thickness away from a top surface of the channel layer, the thickness being within a predetermined thickness range, annealing the III-N device in a gas ambient including oxygen at an elevated temperature to oxidize the remaining portion of the barrier layer in the first portion of the device, and removing the oxidized remaining portion of the barrier layer in the first portion of the device.Type: ApplicationFiled: March 9, 2016Publication date: June 30, 2016Inventors: Mo Wu, Rakesh K. Lal, Ilan Ben-Yaacov, Umesh Mishra, Carl Joseph Neufeld
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Patent number: 9318593Abstract: A method of fabricating a III-N device includes forming a III-N channel layer on a substrate, a III-N barrier layer on the channel layer, an insulator layer on the barrier layer, and a trench in a first portion of the device. Forming the trench comprises removing the insulator layer and a part of the barrier layer in the first portion of the device, such that a remaining portion of the barrier layer in the first portion of the device has a thickness away from a top surface of the channel layer, the thickness being within a predetermined thickness range, annealing the III-N device in a gas ambient including oxygen at an elevated temperature to oxidize the remaining portion of the barrier layer in the first portion of the device, and removing the oxidized remaining portion of the barrier layer in the first portion of the device.Type: GrantFiled: November 17, 2014Date of Patent: April 19, 2016Assignee: Transphorm Inc.Inventors: Mo Wu, Rakesh K. Lal, Ilan Ben-Yaacov, Umesh Mishra, Carl Joseph Neufeld
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Publication number: 20160020313Abstract: A method of fabricating a III-N device includes forming a III-N channel layer on a substrate, a III-N barrier layer on the channel layer, an insulator layer on the barrier layer, and a trench in a first portion of the device. Forming the trench comprises removing the insulator layer and a part of the barrier layer in the first portion of the device, such that a remaining portion of the barrier layer in the first portion of the device has a thickness away from a top surface of the channel layer, the thickness being within a predetermined thickness range, annealing the III-N device in a gas ambient including oxygen at an elevated temperature to oxidize the remaining portion of the barrier layer in the first portion of the device, and removing the oxidized remaining portion of the barrier layer in the first portion of the device.Type: ApplicationFiled: November 17, 2014Publication date: January 21, 2016Inventors: Mo Wu, Rakesh K. Lal, Ilan Ben-Yaacov, Umesh Mishra, Carl Joseph Neufeld
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Publication number: 20150287785Abstract: An N-polar III-N transistor includes a III-N buffer layer, a first III-N barrier layer, and a III-N channel layer, the III-N channel layer having a gate region and a plurality of access regions on opposite sides of the gate region. The compositional difference between the first III-N barrier layer and the III-N channel layer causes a conductive channel to be induced in the access regions of the III-N channel layer. The transistor also includes a source, a gate, a drain, and a second III-N barrier layer between the gate and the III-N channel layer. The second III-N barrier layer has an N-face proximal to the gate and a group-III face opposite the N-face, and has a larger bandgap than the III-N channel layer. The lattice constant of the first III-N barrier layer is within 0.5% of the lattice constant of the buffer layer.Type: ApplicationFiled: June 19, 2015Publication date: October 8, 2015Inventors: Umesh Mishra, Srabanti Chowdhury, Carl Joseph Neufeld
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Patent number: 9093366Abstract: An N-polar III-N transistor includes a III-N buffer layer, a first III-N barrier layer, and a III-N channel layer, the III-N channel layer having a gate region and a plurality of access regions on opposite sides of the gate region. The compositional difference between the first III-N barrier layer and the III-N channel layer causes a conductive channel to be induced in the access regions of the III-N channel layer. The transistor also includes a source, a gate, a drain, and a second III-N barrier layer between the gate and the III-N channel layer. The second III-N barrier layer has an N-face proximal to the gate and a group-III face opposite the N-face, and has a larger bandgap than the III-N channel layer. The lattice constant of the first III-N barrier layer is within 0.5% of the lattice constant of the buffer layer.Type: GrantFiled: April 9, 2013Date of Patent: July 28, 2015Assignee: Transphorm Inc.Inventors: Umesh Mishra, Srabanti Chowdhury, Carl Joseph Neufeld
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Publication number: 20130264578Abstract: An N-polar III-N transistor includes a III-N buffer layer, a first III-N barrier layer, and a III-N channel layer, the III-N channel layer having a gate region and a plurality of access regions on opposite sides of the gate region. The compositional difference between the first III-N barrier layer and the III-N channel layer causes a conductive channel to be induced in the access regions of the III-N channel layer. The transistor also includes a source, a gate, a drain, and a second III-N barrier layer between the gate and the III-N channel layer. The second III-N barrier layer has an N-face proximal to the gate and a group-III face opposite the N-face, and has a larger bandgap than the III-N channel layer. The lattice constant of the first III-N barrier layer is within 0.5% of the lattice constant of the buffer layer.Type: ApplicationFiled: April 9, 2013Publication date: October 10, 2013Applicant: TRANSPHORM INC.Inventors: Umesh Mishra, Srabanti Chowdhury, Carl Joseph Neufeld