Abstract: A microprogrammed processor in which control signals for data paths, the ALU function, the shifter and all other control signals are derived from the current microprogram control word which is normally periodically clocked into a ROM buffer. The processor provides for microbranching capability with and/or without a test, testing capabilities including direct addressing with simultaneous temporary address storage capability for future recall, and selective testing of computer instruction bits for decoding to address the next micro-instruction. Additional capabilities provide for flexible access to the micro-code instruction control store through a ROM address multiplexer which allows for selection of at least one of four possible micro-instruction addresses determined by micro-code control decode logic.