Patents by Inventor Carl Kyono

Carl Kyono has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Structure to reduce signal cross-talk through semiconductor substrate for system on chip applications
    Patent number: 7052939
    Abstract: A structure that reduces signal cross-talk through the semiconductor substrate for System-On-Chip (SOC) (2) applications, thereby facilitating the integration of digital circuit blocks (6) and analog circuit blocks (8) onto a single IC. Cross-circuit interaction through a substrate (4) is reduced by strategically positioning the various digital circuit blocks (6) and analog circuit blocks (8) in an isolated wells (10), (12), (16) and (20) over a resistive substrate (4). These well structures (10), (12), (16), and (20) are then surrounded with a patterned low resistivity layer (22) and optional trench region (24). The patterned low resistivity region (22) is formed below wells (10) and (12) and functions as a low resistance AC ground plane. This low resistivity region (22) collects noise signals that propagate between digital circuit blocks (6) and analog circuit blocks (8).
    Type: Grant
    Filed: November 26, 2002
    Date of Patent: May 30, 2006
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Wen Ling M. Huang, Sushil Bharatan, Carl Kyono, David J. Monk, Kun-Hin To, Pamela J. Welch
  • Structure to reduce signal cross-talk through semiconductor substrate for system on chip applications
    Publication number: 20040099878
    Abstract: A structure that reduces signal cross-talk through the semiconductor substrate for System-On-Chip (SOC) (2) applications, thereby facilitating the integration of digital circuit blocks (6) and analog circuit blocks (8) onto a single IC. Cross-circuit interaction through a substrate (4) is reduced by strategically positioning the various digital circuit blocks (6) and analog circuit blocks (8) in an isolated wells (10), (12), (16) and (20) over a resistive substrate (4). These well structures (10), (12), (16), and (20) are then surrounded with a patterned low resistivity layer (22) and optional trench region (24). The patterned low resistivity region (22) is formed below wells (10) and (12) and functions as a low resistance AC ground plane. This low resistivity region (22) collects noise signals that propagate between digital circuit blocks (6) and analog circuit blocks (8).
    Type: Application
    Filed: November 26, 2002
    Publication date: May 27, 2004
    Applicant: Motorola, Inc.
    Inventors: Wen Ling M. Huang, Sushil Bharatan, Carl Kyono, David J. Monk, Kun-Hin To, Pamela J. Welch