Patents by Inventor Carl L. Deppisch

Carl L. Deppisch has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10651108
    Abstract: Devices and methods disclosed herein can include a conductive foam having pores disposed within the conductive foam. The conductive foam can be compressible between an uncompressed thickness and a compressed thickness. The compressed thickness can be ninety-five percent or less of the uncompressed thickness. In one example, a filler can be disposed in the pores of the conductive foam. The filler can include a first thermal conductivity. The first thermal conductivity can be greater than a thermal conductivity of air.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: May 12, 2020
    Assignee: Intel Corporation
    Inventors: Zhizhong Tang, Syadwad Jain, Wei Hu, Michael A. Schroeder, Rajen S. Sidhu, Carl L. Deppisch, Patrick Nardi, Kelly P. Lofgreen, Manish Dubey
  • Patent number: 10049971
    Abstract: An apparatus is described that includes a substrate and a mold compound disposed on the substrate. The semiconductor die is embedded within the mold compound and is electrically coupled to lands on the substrate. Solder balls are disposed around the semiconductor die on the substrate. Each of the solder balls have a solid coating thereon. The solid coating contains a cleaning agent to promote its solder ball's coalescence with another solder ball. Respective vias are formed in the mold compound that expose the solder balls and their respective solid coatings. In combined or alternate embodiments outer edges of the mold compound have smaller thickness than regions of the mold compound between the vias and the semiconductor die. In combined or alternate embodiments micro-channels exist between the solder balls and the mold compound.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: August 14, 2018
    Assignee: Intel Corporation
    Inventors: Thomas J. De Bonis, Lilia May, Rajen S. Sidhu, Mukul P. Renavikar, Ashay A. Dani, Edward R. Prack, Carl L. Deppisch, Anna M. Prakash, James C. Matayabas, Jason Jieping Zhang, Srinivasa R. Aravamudhan, Chang Lin
  • Publication number: 20180005917
    Abstract: Devices and methods disclosed herein can include a conductive foam having pores disposed within the conductive foam. The conductive foam can be compressible between an uncompressed thickness and a compressed thickness. The compressed thickness can be ninety-five percent or less of the uncompressed thickness. In one example, a filler can be disposed in the pores of the conductive foam. The filler can include a first thermal conductivity. The first thermal conductivity can be greater than a thermal conductivity of air.
    Type: Application
    Filed: June 29, 2016
    Publication date: January 4, 2018
    Inventors: Zhizhong Tang, Syadwad Jain, Wei Hu, Michael A. Schroeder, Rajen S. Sidhu, Carl L. Deppisch, Patrick Nardi, Kelly P. Lofgreen
  • Patent number: 9808875
    Abstract: Methods and associated structures of forming a package structure including forming a low melting point solder material on a solder resist opening location of an IHS keep out zone, forming a sealant in a non SRO keep out zone region; attaching the IHS to the sealant, and curing the sealant, wherein a solder joint is formed between the IHS and the low melting point solder material.
    Type: Grant
    Filed: February 5, 2016
    Date of Patent: November 7, 2017
    Assignee: Intel Corporation
    Inventors: Deepak V. Kulkarni, Carl L. Deppisch, Leonel R. Arana, Gregory S. Constable, Sriram Srinivasan
  • Publication number: 20170207152
    Abstract: An apparatus is described that includes a substrate and a mold compound disposed on the substrate. The semiconductor die is embedded within the mold compound and is electrically coupled to lands on the substrate. Solder balls are disposed around the semiconductor die on the substrate. Each of the solder balls have a solid coating thereon. The solid coating contains a cleaning agent to promote its solder ball's coalescence with another solder ball. Respective vias are formed in the mold compound that expose the solder balls and their respective solid coatings. In combined or alternate embodiments outer edges of the mold compound have smaller thickness than regions of the mold compound between the vias and the semiconductor die. In combined or alternate embodiments micro-channels exist between the solder balls and the mold compound.
    Type: Application
    Filed: April 3, 2017
    Publication date: July 20, 2017
    Inventors: Thomas J. De Bonis, Lilia May, Rajen S. Sidhu, Mukul P. Renavikar, Ashay A. Dani, Edward R. Prack, Carl L. Deppisch, Anna M. Prakash, James C. Matayabas, Jason Jieping Zhang, Srinivasa R. Aravamudhan, Chang Lin
  • Patent number: 9613933
    Abstract: An apparatus is described that includes a substrate and a mold compound disposed on the substrate. The semiconductor die is embedded within the mold compound and is electrically coupled to lands on the substrate. Solder balls are disposed around the semiconductor die on the substrate. Each of the solder balls have a solid coating thereon. The solid coating contains a cleaning agent to promote its solder ball's coalescence with another solder ball. Respective vias are formed in the mold compound that expose the solder balls and their respective solid coatings. In combined or alternate embodiments outer edges of the mold compound have smaller thickness than regions of the mold compound between the vias and the semiconductor die. In combined or alternate embodiments micro-channels exist between the solder balls and the mold compound.
    Type: Grant
    Filed: March 5, 2014
    Date of Patent: April 4, 2017
    Assignee: Intel Corporation
    Inventors: Thomas J. De Bonis, Lilia May, Rajen S. Sidhu, Mukul P. Renavikar, Ashay A. Dani, Edward R. Prack, Carl L. Deppisch, Anna M. Prakash, James C. Matayabas, Jr., Jason Jieping Zhang, Srinivasa R. Aravamudhan, Chang Lin
  • Publication number: 20170053858
    Abstract: Embodiments herein may relate to a patch on interposer (PoINT) architecture. In embodiments, the PoINT architecture may include a plurality of solder joints between a patch and an interposer. The solder joints may include a relatively high temperature solder ball and a relatively low temperature solder paste that at least partially surrounds the solder ball. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: August 20, 2015
    Publication date: February 23, 2017
    Inventors: Jan Krajniak, Carl L. Deppisch, Kabirkumar J. Mirpuri, Hongjin Jiang, Fay Hua, Yuying Wei, Beverly J. Canham, Jiongxin Lu, Mukul P. Renavikar
  • Publication number: 20160151850
    Abstract: Methods and associated structures of forming a package structure including forming a low melting point solder material on a solder resist opening location of an IHS keep out zone, forming a sealant in a non SRO keep out zone region; attaching the IHS to the sealant, and curing the sealant, wherein a solder joint is formed between the IHS and the low melting point solder material.
    Type: Application
    Filed: February 5, 2016
    Publication date: June 2, 2016
    Inventors: Deepak V. Kulkarni, Carl L. Deppisch, Leonel R. Arana, Gregory S. Constable, Sriram Srinivasan
  • Patent number: 9330999
    Abstract: A multi-component heat spreader comprising a top component having a first surface and an opposing second surface with either a cavity extending therein from the second surface thereof or a projection extending from the second surface thereof. The multi-component heat spreader further includes at least one additional component, such as a footing component or a spacer component, having a first surface and an opposing second surface with either a cavity extending therein from the second surface thereof or a projection extending from the second surface thereof, which is opposite from the top component cavity/projection. The additional component is attached to the top component, such as by brazing, wherein the top component cavity/projection is mated to the additional component cavity/projection.
    Type: Grant
    Filed: June 5, 2014
    Date of Patent: May 3, 2016
    Assignee: Intel Corporation
    Inventors: Thomas J. Fitzgerald, Aravindha R. Antoniswamy, Carl L. Deppisch, Nikunj P. Patel
  • Patent number: 9257405
    Abstract: Embodiments of the present disclosure are directed towards multi-solder techniques and configurations for integrated circuit (IC) package assembly. In one embodiment, a method includes depositing a plurality of solder balls on a plurality of pads of a package substrate, the plurality of solder balls corresponding with the plurality of pads and performing a solder reflow process to form a solder joint between the plurality of solder balls and the plurality of pads. Individual solder balls of the plurality of solder balls include a first solder material and a second solder material, the first solder material having a liquidus temperature that is greater than a peak temperature of the solder reflow process and the second solder material having a liquidus temperature that is less than the peak temperature of the solder reflow process. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: July 10, 2014
    Date of Patent: February 9, 2016
    Assignee: Intel Corporation
    Inventors: Rajen S. Sidhu, Wei Hu, Carl L. Deppisch, Martha A. Dudek
  • Patent number: 9254532
    Abstract: Methods and associated structures of forming a package structure including forming a low melting point solder material on a solder resist opening location of an IHS keep out zone, forming a sealant in a non SRO keep out zone region; attaching the IHS to the sealant, and curing the sealant, wherein a solder joint is formed between the IHS and the low melting point solder material.
    Type: Grant
    Filed: December 30, 2009
    Date of Patent: February 9, 2016
    Assignee: Intel Corporation
    Inventors: Deepak V. Kulkarni, Carl L. Deppisch, Leonel R. Arana, Gregory S. Constable, Sriram Srinivasan
  • Publication number: 20150357258
    Abstract: A multi-component heat spreader comprising a top component having a first surface and an opposing second surface with either a cavity extending therein from the second surface thereof or a projection extending from the second surface thereof. The multi-component heat spreader further includes at least one additional component, such as a footing component or a spacer component, having a first surface and an opposing second surface with either a cavity extending therein from the second surface thereof or a projection extending from the second surface thereof, which is opposite from the top component cavity/projection. The additional component is attached to the top component, such as by brazing, wherein the top component cavity/projection is mated to the additional component cavity/projection.
    Type: Application
    Filed: June 5, 2014
    Publication date: December 10, 2015
    Applicant: Intel Corporation
    Inventors: Thomas J. Fitzgerald, Aravindha R. Antoniswamy, Carl L. Deppisch, Nikunj P. Patel
  • Publication number: 20150255415
    Abstract: An apparatus is described that includes a substrate and a mold compound disposed on the substrate. The semiconductor die is embedded within the mold compound and is electrically coupled to lands on the substrate. Solder balls are disposed around the semiconductor die on the substrate. Each of the solder balls have a solid coating thereon. The solid coating contains a cleaning agent to promote its solder ball's coalescence with another solder ball. Respective vias are formed in the mold compound that expose the solder balls and their respective solid coatings. In combined or alternate embodiments outer edges of the mold compound have smaller thickness than regions of the mold compound between the vias and the semiconductor die. In combined or alternate embodiments micro-channels exist between the solder balls and the mold compound.
    Type: Application
    Filed: March 5, 2014
    Publication date: September 10, 2015
    Inventors: Thomas J. De Bonis, Lilia May, Rajen S. Sidhu, Mukul P. Renavikar, Ashay A. Dani, Edward R. Prack, Carl L. Deppisch, Anna M. Prakash, James C. Matayabas, JR., Jason Jieping Zhang, Srinivasa R. Aravamudhan, Chang Lin
  • Publication number: 20140319682
    Abstract: Embodiments of the present disclosure are directed towards multi-solder techniques and configurations for integrated circuit (IC) package assembly. In one embodiment, a method includes depositing a plurality of solder balls on a plurality of pads of a package substrate, the plurality of solder balls corresponding with the plurality of pads and performing a solder reflow process to form a solder joint between the plurality of solder balls and the plurality of pads. Individual solder balls of the plurality of solder balls include a first solder material and a second solder material, the first solder material having a liquidus temperature that is greater than a peak temperature of the solder reflow process and the second solder material having a liquidus temperature that is less than the peak temperature of the solder reflow process. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: July 10, 2014
    Publication date: October 30, 2014
    Inventors: Rajen S. Sidhu, Wei Hu, Carl L. Deppisch, Martha A. Dudek
  • Patent number: 8809181
    Abstract: Embodiments of the present disclosure are directed towards multi-solder techniques and configurations for integrated circuit (IC) package assembly. In one embodiment, a method includes depositing a plurality of solder balls on a plurality of pads of a package substrate, the plurality of solder balls corresponding with the plurality of pads and performing a solder reflow process to form a solder joint between the plurality of solder balls and the plurality of pads. Individual solder balls of the plurality of solder balls include a first solder material and a second solder material, the first solder material having a liquidus temperature that is greater than a peak temperature of the solder reflow process and the second solder material having a liquidus temperature that is less than the peak temperature of the solder reflow process. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: November 7, 2012
    Date of Patent: August 19, 2014
    Assignee: Intel Corporation
    Inventors: Rajen S. Sidhu, Wei Hu, Carl L. Deppisch, Martha A. Dudek
  • Publication number: 20140124925
    Abstract: Embodiments of the present disclosure are directed towards multi-solder techniques and configurations for integrated circuit (IC) package assembly. In one embodiment, a method includes depositing a plurality of solder balls on a plurality of pads of a package substrate, the plurality of solder balls corresponding with the plurality of pads and performing a solder reflow process to form a solder joint between the plurality of solder balls and the plurality of pads. Individual solder balls of the plurality of solder balls include a first solder material and a second solder material, the first solder material having a liquidus temperature that is greater than a peak temperature of the solder reflow process and the second solder material having a liquidus temperature that is less than the peak temperature of the solder reflow process. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: November 7, 2012
    Publication date: May 8, 2014
    Inventors: Rajen S. Sidhu, Wei Hu, Carl L. Deppisch, Martha A. Dudek
  • Patent number: 8550327
    Abstract: A clad solder thermal interface material is described. In one example the material has a a first layer of solder having a melting temperature lower than a temperature of a particular solder reflow furnace, a second layer of solder clad to the first layer of solder, the second layer having a melting temperature higher than the temperature of the solder reflow furnace, and a third layer of solder clad to the second layer of solder opposite the first layer, the third layer having a melting temperature lower than the temperature of the solder reflow furnace.
    Type: Grant
    Filed: February 3, 2011
    Date of Patent: October 8, 2013
    Assignee: Intel Corporation
    Inventors: Carl L. Deppisch, Rajasekaran Swaminathan
  • Publication number: 20110159310
    Abstract: Methods and associated structures of forming a package structure including forming a low melting point solder material on a solder resist opening location of an IHS keep out zone, forming a sealant in a non SRO keep out zone region; attaching the IHS to the sealant, and curing the sealant, wherein a solder joint is formed between the IHS and the low melting point solder material.
    Type: Application
    Filed: December 30, 2009
    Publication date: June 30, 2011
    Inventors: Deepak V. Kulkarni, Carl L. Deppisch, Leonel R. Arana, Gregory S. Constable, Sriram Srinivasan
  • Publication number: 20110147914
    Abstract: A clad solder thermal interface material is described. In one example the material has a a first layer of solder having a melting temperature lower than a temperature of a particular solder reflow furnace, a second layer of solder clad to the first layer of solder, the second layer having a melting temperature higher than the temperature of the solder reflow furnace, and a third layer of solder clad to the second layer of solder opposite the first layer, the third layer having a melting temperature lower than the temperature of the solder reflow furnace.
    Type: Application
    Filed: February 3, 2011
    Publication date: June 23, 2011
    Inventors: Carl L. Deppisch, Rajasekaran Swaminathan
  • Patent number: 7704798
    Abstract: A composite of two or more thermal interface materials (“TIMs”) is placed between a die and a heat spreader to improve cooling of the die in an integrated circuit package. The two or more TIMs vary in heat-dissipation capability depending upon the locations of die hot spots. In an embodiment, a more thermally conductive material may be positioned over one or more die hot spots, and a less thermally conductive material may be positioned abutting and/or surrounding the more thermally conductive material. The two or more TIMs may comprise a solder and a polymer. The composite TIM may be preformed as one unit or as a plurality of units. Methods of fabrication, as well as application of the package to an electronic assembly and to an electronic system, are also described.
    Type: Grant
    Filed: December 8, 2008
    Date of Patent: April 27, 2010
    Assignee: Intel Corporation
    Inventors: Fay Hua, Carl L. Deppisch, Joni G. Hansen, Youzhi E Xu