Patents by Inventor Carl Lemonds

Carl Lemonds has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Bridge fused multiply-adder circuit
    Patent number: 8078660
    Abstract: A bridge fused multiply-adder is disclosed. The fused multiply-adder is for the single instruction execution of (A×B)+C. The bridge fused multiply-add unit adds this functionality to existing floating-point co-processor units by including a fused multiply-add hardware “bridge” between an existing floating-point adder and a floating-point multiplier unit. This fused multiply-add functionality is added to existing two-operand architecture designs without degrading the performance or parallel pipe execution of floating-point adder and floating-point multiplier instructions.
    Type: Grant
    Filed: April 9, 2008
    Date of Patent: December 13, 2011
    Assignee: The Board of Regents, University of Texas System
    Inventors: Eric Quinnell, Earl E. Swartzlander, Jr., Carl Lemonds
  • Three-path fused multiply-adder circuit
    Patent number: 8037118
    Abstract: A three-path floating-point fused multiply-adder is disclosed. The fused multiply-adder is for the single instruction execution of (A×B)+C. The three-path fused multiply-adder is based on a dual-path adder and reduces latency significantly by operating on case data in parallel and by reducing component bit size. The fused multiply-adder is a common serial fused multiply-adder that reuses floating-point adder (FPA) and floating-point multiplier (FPM) hardware, allowing single adds, single multiplies, and fused multiply-adds to execute at maximum speed.
    Type: Grant
    Filed: April 9, 2008
    Date of Patent: October 11, 2011
    Inventors: Eric Quinnell, Earl E. Swartzlander, Jr., Carl Lemonds
  • Bridge Fused Multiply-Adder Circuit
    Publication number: 20080256161
    Abstract: A bridge fused multiply-adder is disclosed. The fused multiply-adder is for the single instruction execution of (A×B)+C. The bridge fused multiply-add unit adds this functionality to existing floating-point co-processor units by including a fused multiply-add hardware “bridge” between an existing floating-point adder and a floating-point multiplier unit. This fused multiply-add functionality is added to existing two-operand architecture designs without degrading the performance or parallel pipe execution of floating-point adder and floating-point multiplier instructions.
    Type: Application
    Filed: April 9, 2008
    Publication date: October 16, 2008
    Inventors: Eric Quinnell, Earl E. Swartzlander, Carl Lemonds
  • Three-path fused multiply-adder circuit
    Publication number: 20080256150
    Abstract: A three-path floating-point fused multiply-adder is disclosed. The fused multiply-adder is for the single instruction execution of (A×B)+C. The three-path fused multiply-adder is based on a dual-path adder and reduces latency significantly by operating on case data in parallel and by reducing component bit size. The fused multiply-adder is a common serial fused multiply-adder that reuses floating-point adder (FPA) and floating-point multiplier (FPM) hardware, allowing single adds, single multiplies, and fused multiply-adds to execute at maximum speed.
    Type: Application
    Filed: April 9, 2008
    Publication date: October 16, 2008
    Inventors: Eric Quinnell, Earl E. Swartzlander, Carl Lemonds