Abstract: An image sensor may include an array of image pixels arranged in rows and columns. The columns of pixels are coupled to corresponding delta sigma modulators. Each group of delta sigma modulators may be coupled to a column memory circuit. The column memory circuit may receive bits serially from each pixel column in the group. Once all bits in a bit stream from each pixel column have been stored into the column memory circuit, the column memory circuit may output one bit stream at a time to a shared filter circuit. The shared filter circuit may process an entire bit stream associated with a given column in one cycle. Sharing the filter circuit among multiple pixel columns can dramatically reduce circuit area for the image sensor.

Abstract: An image sensor may include an array of image pixels arranged in rows and columns. The columns of pixels are coupled to corresponding delta sigma modulators. Each group of delta sigma modulators may be coupled to a column memory circuit. The column memory circuit may receive bits serially from each pixel column in the group. Once all bits in a bit stream from each pixel column have been stored into the column memory circuit, the column memory circuit may output one bit stream at a time to a shared filter circuit. The shared filter circuit may process an entire bit stream associated with a given column in one cycle. Sharing the filter circuit among multiple pixel columns can dramatically reduce circuit area for the image sensor.

Abstract: An image sensor may include an array of image pixels coupled to analog-to-digital conversion circuitry. To reduce space on the integrated circuit on which the image sensor is formed, the analog-to-digital conversion circuitry may have at least some portions that are shared between columns of the array of image pixels. In particular, individual delta-sigma modulators may be coupled to each column of the pixels to convert the charge generated by the pixels into digital bits, and shared accumulator circuitry may convert the digital bits into a digital signal. The shared accumulator circuitry may use pre-determined weights to reduce the number of required accumulation steps, and sequentially process the bits corresponding to two or more columns of the pixels. The digital signal may be stored in a shift register to further reduce the area required for the analog-to-digital conversion circuitry.