Patents by Inventor Carl Naylor

Carl Naylor has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11018075
    Abstract: An example relates to an integrated circuit including a semiconductor substrate, and a wiring layer stack located on the semiconductor substrate. The integrated circuit further includes a transistor embedded in the wiring layer stack. The transistor includes an embedded layer. The embedded layer has a thickness of less than 10 nm. The embedded layer includes at least one two-dimensional crystalline layer including more than 10% metal atoms. Further examples relate to methods for forming integrated circuits.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: May 25, 2021
    Assignee: Intel Corporation
    Inventors: Carl Naylor, Ashish Agrawal, Kevin Lin, Abhishek Sharma, Mauro Kobrinsky, Christopher Jezewski, Urusa Alaan
  • Publication number: 20210098387
    Abstract: Composite integrated circuit (IC) device structures that include two components coupled through a hybrid bonded composite interconnect structure. The two components may be two different monolithic IC structures (e.g., chips) that are bonded over substantially planar dielectric and metallization interfaces. Composite interconnect metallization features formed at a bond interface may be doped with a metal or chalcogenide dopant. The dopant may migrate to a periphery of the composite interconnect structure and form a barrier material that will then limit outdiffusion of a metal, such as copper, into adjacent dielectric material.
    Type: Application
    Filed: September 27, 2019
    Publication date: April 1, 2021
    Applicant: Intel Corporation
    Inventors: Carl Naylor, Mauro Kobrinsky, Richard Vreeland, Ramanan Chebiam, William Brezinski, Brennen Mueller, Jeffery Bielefeld
  • Publication number: 20210090991
    Abstract: Integrated circuit structures having linerless self-forming barriers, and methods of fabricating integrated circuit structures having linerless self-forming barriers, are described. In an example, an integrated circuit structure includes a dielectric material above a substrate. An interconnect structure is in a trench in the dielectric material. The interconnect structure includes a conductive fill material and a two-dimensional (2D) crystalline liner. The 2D crystalline liner is in direct contact with the dielectric material and with the conductive fill material. The 2D crystalline liner includes a same metal species as the conductive fill material.
    Type: Application
    Filed: September 24, 2019
    Publication date: March 25, 2021
    Inventors: Abhishek A. SHARMA, Carl NAYLOR, Urusa ALAAN
  • Publication number: 20210083122
    Abstract: Transistor structures with a channel semiconductor material that is passivated with two-dimensional (2D) crystalline material. The 2D material may comprise a semiconductor having a bandgap offset from a band of the channel semiconductor. The 2D material may be a thin as a few monolayers and have good temperature stability. The 2D material may be a conversion product of a sacrificial precursor material, or of a portion of the channel semiconductor material. The 2D material may comprise one or more metal and a chalcogen. The channel material may be a metal oxide semiconductor suitable for low temperature processing (e.g., IGZO), and the 2D material may also be compatible with low temperature processing (e.g., <450° C.). The 2D material may be a chalcogenide of a metal present in the channel material (e.g., ZnSx or ZnSex) or of a metal absent from the channel material when formed from a sacrificial precursor.
    Type: Application
    Filed: September 13, 2019
    Publication date: March 18, 2021
    Applicant: Intel Corporation
    Inventors: Carl Naylor, Abhishek Sharma, Mauro Kobrinsky, Christopher Jezewski, Urusa Alaan, Justin Weber
  • Publication number: 20200388685
    Abstract: Transistor structures employing metal chalcogenide channel materials may be formed where a chalcogen is introduced into at least a portion of a precursor material that comprises reactive metal(s). The precursor material may be substantially metallic, or may be a metallic oxide (e.g., an oxide semiconductor). The metal(s) may be transition, Group II, Group III, Group V elements, or alloys thereof. An oxide of one or more such metals (e.g., IGZO) may be converted into a chalcogenide (e.g., IGZSx or IGZSex) having semiconducting properties. The chalcogenide formed in this manner may be only a few monolayers in thickness (and may be more thermally stable than many oxide semiconductors. Where not all of the precursor material is converted, a transistor structure may retain the precursor material, for example as part of a transistor channel or a gate dielectric. Backend transistors including metal chalcogenide channel materials may be fabricated over silicon CMOS circuitry.
    Type: Application
    Filed: June 7, 2019
    Publication date: December 10, 2020
    Applicant: Intel Corporation
    Inventors: Abhishek A. Sharma, Ashish Agarwal, Urusa Alaan, Christopher Jezewski, Kevin Lin, Carl Naylor
  • Publication number: 20200219804
    Abstract: Integrated circuits including selectable vias are disclosed. The techniques are particularly well-suited to back end of line (BEOL) processes. In accordance with some embodiments, a selectable via includes a vertically-oriented thin film transistor structure having a wrap around gate, which can be used to effectively select (or deselect) the selectable via ad hoc. When a selectable via is selected, a signal is allowed to pass through the selectable via. Conversely, when the selectable via is not selected, a signal is not allowed to pass through the selectable via. The selectable characteristic of the selectable via allows multiple vias to share a global interconnect. The global interconnect can be connected to any number of selectable vias, as well as standard vias.
    Type: Application
    Filed: January 9, 2019
    Publication date: July 9, 2020
    Applicant: Intel Corporation
    Inventors: Christopher Jezewski, Ashish Agrawal, Kevin L. Lin, Abhishek Sharma, Carl Naylor, Urusa Alaan
  • Publication number: 20200194338
    Abstract: An example relates to an integrated circuit including a semiconductor substrate, and a wiring layer stack located on the semiconductor substrate. The integrated circuit further includes a transistor embedded in the wiring layer stack. The transistor includes an embedded layer. The embedded layer has a thickness of less than 10 nm. The embedded layer includes at least one two-dimensional crystalline layer including more than 10% metal atoms. Further examples relate to methods for forming integrated circuits.
    Type: Application
    Filed: December 17, 2018
    Publication date: June 18, 2020
    Inventors: Carl NAYLOR, Ashish AGRAWAL, Kevin LIN, Abhishek Sharma, Mauro KOBRINSKY, Christopher JEZEWSKI, Urusa ALAAN
  • Publication number: 20200194376
    Abstract: An aspect of the disclosure relates to an integrated circuit. The integrated circuit includes a first electrically conductive structure, a thin film crystal layer located on the first electrically conductive structure, and a second electrically conductive structure including metal e.g. copper. The second electrically conductive structure is located on the thin film crystal layer. The first electrically conductive structure is electrically connected to the second electrically conductive structure through the thin film crystal layer. The thin film crystal layer may be provided as a copper diffusion barrier.
    Type: Application
    Filed: December 17, 2018
    Publication date: June 18, 2020
    Inventors: Carl NAYLOR, Ashish AGRAWAL, Kevin LIN, Abhishek SHARMA, Mauro KOBRINSKY, Christopher JEZEWSKI, Urusa ALAAN
  • Publication number: 20200185532
    Abstract: A transistor structure includes a layer of active material on a base. The base can be insulator material in some cases. The layer has a channel region between a source region and a drain region. A gate structure is in contact with the channel region and includes a gate electrode and a gate dielectric, where the gate dielectric is between the gate electrode and the active material. An electrical contact is on one or both of the source region and the drain region. The electrical contact has a larger portion in contact with a top surface of the active material and a smaller portion extending through the layer of active material into the base. The active material may be, for example, a transition metal dichalcogenide (TMD) in some embodiments.
    Type: Application
    Filed: December 10, 2018
    Publication date: June 11, 2020
    Applicant: INTEL CORPORATION
    Inventors: Kevin Lin, Abhishek Sharma, Carl Naylor, Urusa Alaan, Christopher Jezewski, Ashish Agrawal
  • Patent number: 4281230
    Abstract: In a magnetic particle testing procedure, a spring loaded prod with contact points prevents arc strikes from occurring between the prod and a part under test. Positive pressure is applied to the prod which engages the contacts before current can flow to the part. Similarly, in removing the prod from the part with the prod power switch depressed, the arcing will occur in the prod assembly and not on the part under test.
    Type: Grant
    Filed: October 4, 1979
    Date of Patent: July 28, 1981
    Assignee: Allis-Chalmers Corporation
    Inventor: Carl A. Naylor
  • Patent number: 4219772
    Abstract: A pair of electrical prods along with a powder supply gun are incorporated in a single portable frame member which is easily insertable into a relatively small blind bore; prod tension against the bore wall is adjustable by varying spring plunger tension; incorporated in the apparatus is the ability to locate indications in all directions by provision of both linear and axial heads which interchange on the same frame or handle; powder is applied to the area to be inspected while current is flowing into the prods, and the powder gun can be rotated and retracted as required to provide full coverage of the area to be inspected with powder.
    Type: Grant
    Filed: July 25, 1978
    Date of Patent: August 26, 1980
    Assignee: Allis-Chalmers Corporation
    Inventor: Carl A. Naylor