Abstract: Methods and apparatus are provided for modeling signal delays in a metastability protection circuit. A metastability protection circuit that processes a signal that crosses between two clock domains is modeled by introducing a random transition delay into the signal upon detection of an edge in the signal. Thereafter, an effect of the random transition delay on one or more downstream logic elements can be evaluated. The random transition delay simulates a timing effect of a metastable state. The random transition delay can optionally be introduced only during a simulation stage of the metastability protection circuit. For example, the metastability protection circuit can be defined using a Register Transfer Language and the Register Transfer Language includes one or more statements that selectively allow the introducing step.

Abstract: A modulo address generation circuit for generating multiple-word memory accesses for use in a computer system. The circuit includes an address pointer latch for retaining a current address pointer, an adder for receiving the current address pointer as a first input and a displacement as a second input. The adder for adding the inputs to provide an output. A comparator compares the current address pointer to an ending address of a circular buffer ignoring least significant bits thereof when the displacement is greater than one. The comparator provides an output that is a first state when the inputs are the same and an output that is a second state when the outputs are different. A control circuit is adapted to receive an indicator of the beginning address of the circular buffer, an indicator of the current address pointer, and an indicator of the ending address of the circular buffer.