Abstract: A signal processing circuit (10) generates a bias signal (27) that is used for biasing a comparator (26). An input signal (14) is compared to the bias signal (27) in order to reconstruct the input signal (14) on an output of the comparator. The bias signal (27) is generated by selecting the larger of a percent of the input signal (23) or an offset signal (24) that is larger than a minimum value of the input signal.

Abstract: A phase acquisition and tracking apparatus in which a phase difference between a reference signal and a signal to be acquired is rotated within a negative feedback loop so that such phase difference disappears is disclosed. In another embodiment, a baseband signal which is influenced by such a phase difference is rotated within a negative feedback loop so that the phase difference disappears. The phase rotated signal serves as an output signal from the phase acquisition and tracking apparatus, and this output signal faithfully and rapidly reproduces the input signal regardless of any particular value of such phase difference. Since a negative feedback loop is used to control the amount of phase rotation, non-linearities and other errors produced by multipliers, summing devices and combining circuits are automatically compensated for through the feedback.

Abstract: An apparatus and method is disclosed of an SMSK/2 device that provides an additional phase state, and having at least three phase changes possible per bit period, as compared with standard SMSK/2 devices. The additional phase state increases the bit time needed for the signals to remerge which increases the euclidean distance defined by the remergence paths. The increase in euclidean distance provides an improved power efficiency and bit error rate (BER).

Abstract: A signal probe that does not require a direct ground contact is disclosed. The probe consists of a resistive measuring tip, an amplifier and a probe body which acts as an antenna providing a ground reference for the probe. The frequency of the signal measured may be compensated for by adjusting the resistive tip in the probe which varies the shunt capacitance between the resistor and the probe body.

Abstract: An apparatus and method is disclosed of an SMSK/N concept that utilizes a divide-by-N device in the modulator and a multiply-by-N device in the demodulator to provide improved bandwidth efficiency over conventional SMSK devices. This apparatus provides reduced bandwidth without an excessive increase in the power required for transmission.

Abstract: SMSK data link degradation in future and immediate past bits produced by carrier phase error and small errors in the sampling instant are reduced by a recursive adaptive equalizer having a feedforward stage with adjustable weight for each future bit to be corrected and a feedback stage with adjustable weight for each immediate past bit to be corrected. The weights are controlled by a controller which samples the output and adjusts each weight until the output is correct.

Abstract: An SMSK or MSK demodulator utilizing a Costas type closed loop wherein the voltage controlled oscillator is offset from the apparent carrier frequency of the SMSK or MSK signals so that the in-phase arm of the loop provides data at the output and the quadrature arm of the loop provides an indication that the loop is locked and, in combination with the data output, provides a control signal for the VCO which maintains the loop locked.

Abstract: An SMSK modulator wherein the output of a bi-phase modulator is passed through a notch filter and a band pass filter to produce an SMSK signal for transmission. The notch filter and band pass filter are constructed to simulate the output (center lobe) of an SMSK conversion filter, which is defined as a filter that converts a bi-phase shift keyed (BPSK) modulated signal into MSK.

Abstract: A shift keyed phase detector having a first input for receiving a signal including data shift keyed modulated on a carrier, such as BPSK, QPSK, MSK, SMSK, etc., and a second input for receiving a reference frequency from a local oscillator, to supply in-phase and quadrature channel data signals at differing phase error angles relative to the local oscillator reference frequency. The in-phase and quadrature channel signals are squared, and the squared signals are summed and filtered to provide a first phase error signal. The in-phase and quadrature channel signals are also multiplied with each other and filtered to provide a second phase error signal. The in-phase and quadrature channel signals are cross-multiplied with each of the phase error signals and then combined to provide a data signal in phase with the original data signal.

Abstract: A stream of demodulated data is converted to unidirectional pulses, multiplied by two clock reference signals separated by 90 degrees to form two products, which products are low pass filtered and cross multiplied by the same two clock reference signals, and the products produced are summed together to provide a clock reference which is in-phase with the switching times of the data pulses. The in-phase clock pulses operate a sampling circuit to sample the data at each switching point.

Abstract: A received, suppressed carrier, quadraphase shift key modulated (QPSK) signal is demodulated with a phase locked loop including a variable frequency, coherent reference that drives first and second channels also responsive to the QPSK signal. The channels respectively derive first and second replicas of binary signals that modulated the suppressed carrier. The replicas are combined to derive a variable amplitude error signal for controlling the coherent reference frequency. The frequency of the coherent reference is dithered at a low rate so that there is derived a relatively low level tracking error phase from the locked loop. The frequency of the coherent reference is swept when the phase of the error signal differs from the dithering phase by a predetermined value that is appreciably less than 90.degree..

Abstract: An improved quadraphase shift keyed (QPSK) adaptive demodulator includes a Costas loop modified to independently cross couple the inphase (I) and quadraphase (.phi.) channels so that minimum cross talk takes place between the I and Q channels. Advantageously, the improved QPSK adaptive demodulator separates the feedback control for correcting the phasor errors in the I and Q phasors. Advantageously, the improved demodulator permits independent phase adjustment of the I and Q demodulator outputs.

Abstract: A quadriphase shift keyed (QPSK) adaptive equalizer includes baseband inphase (I) and quadrature (Q) adaptive filters for receiving demodulated OPSK signals. The I and Q channel filters are designed to operate independent of each other and adapt their characteristics continuously in a predetermined manner in response to an incoming received QPSK signal, distorted in an unknown time varying manner.